Lines Matching +full:rx +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
52 /* Tx time-slot assignment table pointer (16 bits) */
54 /* Rx pointer (16 bits) */
64 /* Rx time-slot assignment table pointer (16 bits) */
70 /* Time slot assignment table Rx (32 x 16 bits) */
102 /* Zero-insertion state (32 bits) */
106 /* Rx buffer descriptor base address (16 bits, offset from MCBASE) */
112 /* Rx internal state (32 bits) */
114 /* Rx buffer descriptor pointer (16 bits) */
273 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &tsa_info); in qmc_chan_get_info()
277 spin_lock_irqsave(&chan->ts_lock, flags); in qmc_chan_get_info()
279 info->mode = chan->mode; in qmc_chan_get_info()
280 info->rx_fs_rate = tsa_info.rx_fs_rate; in qmc_chan_get_info()
281 info->rx_bit_rate = tsa_info.rx_bit_rate; in qmc_chan_get_info()
282 info->nb_tx_ts = hweight64(chan->tx_ts_mask); in qmc_chan_get_info()
283 info->tx_fs_rate = tsa_info.tx_fs_rate; in qmc_chan_get_info()
284 info->tx_bit_rate = tsa_info.tx_bit_rate; in qmc_chan_get_info()
285 info->nb_rx_ts = hweight64(chan->rx_ts_mask); in qmc_chan_get_info()
287 spin_unlock_irqrestore(&chan->ts_lock, flags); in qmc_chan_get_info()
297 spin_lock_irqsave(&chan->ts_lock, flags); in qmc_chan_get_ts_info()
299 ts_info->rx_ts_mask_avail = chan->rx_ts_mask_avail; in qmc_chan_get_ts_info()
300 ts_info->tx_ts_mask_avail = chan->tx_ts_mask_avail; in qmc_chan_get_ts_info()
301 ts_info->rx_ts_mask = chan->rx_ts_mask; in qmc_chan_get_ts_info()
302 ts_info->tx_ts_mask = chan->tx_ts_mask; in qmc_chan_get_ts_info()
304 spin_unlock_irqrestore(&chan->ts_lock, flags); in qmc_chan_get_ts_info()
316 if ((ts_info->rx_ts_mask & chan->rx_ts_mask_avail) != ts_info->rx_ts_mask) in qmc_chan_set_ts_info()
317 return -EINVAL; in qmc_chan_set_ts_info()
318 if ((ts_info->tx_ts_mask & chan->tx_ts_mask_avail) != ts_info->tx_ts_mask) in qmc_chan_set_ts_info()
319 return -EINVAL; in qmc_chan_set_ts_info()
321 /* In case of common rx/tx table, rx/tx masks must be identical */ in qmc_chan_set_ts_info()
322 if (chan->qmc->is_tsa_64rxtx) { in qmc_chan_set_ts_info()
323 if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) in qmc_chan_set_ts_info()
324 return -EINVAL; in qmc_chan_set_ts_info()
327 spin_lock_irqsave(&chan->ts_lock, flags); in qmc_chan_set_ts_info()
329 if ((chan->tx_ts_mask != ts_info->tx_ts_mask && !chan->is_tx_stopped) || in qmc_chan_set_ts_info()
330 (chan->rx_ts_mask != ts_info->rx_ts_mask && !chan->is_rx_stopped)) { in qmc_chan_set_ts_info()
331 dev_err(chan->qmc->dev, "Channel rx and/or tx not stopped\n"); in qmc_chan_set_ts_info()
332 ret = -EBUSY; in qmc_chan_set_ts_info()
334 chan->tx_ts_mask = ts_info->tx_ts_mask; in qmc_chan_set_ts_info()
335 chan->rx_ts_mask = ts_info->rx_ts_mask; in qmc_chan_set_ts_info()
338 spin_unlock_irqrestore(&chan->ts_lock, flags); in qmc_chan_set_ts_info()
346 if (param->mode != chan->mode) in qmc_chan_set_param()
347 return -EINVAL; in qmc_chan_set_param()
349 switch (param->mode) { in qmc_chan_set_param()
351 if ((param->hdlc.max_rx_buf_size % 4) || in qmc_chan_set_param()
352 (param->hdlc.max_rx_buf_size < 8)) in qmc_chan_set_param()
353 return -EINVAL; in qmc_chan_set_param()
355 qmc_write16(chan->qmc->scc_pram + QMC_GBL_MRBLR, in qmc_chan_set_param()
356 param->hdlc.max_rx_buf_size - 8); in qmc_chan_set_param()
357 qmc_write16(chan->s_param + QMC_SPE_MFLR, in qmc_chan_set_param()
358 param->hdlc.max_rx_frame_size); in qmc_chan_set_param()
359 if (param->hdlc.is_crc32) { in qmc_chan_set_param()
360 qmc_setbits16(chan->s_param + QMC_SPE_CHAMR, in qmc_chan_set_param()
363 qmc_clrbits16(chan->s_param + QMC_SPE_CHAMR, in qmc_chan_set_param()
369 qmc_write16(chan->s_param + QMC_SPE_TMRBLR, in qmc_chan_set_param()
370 param->transp.max_rx_buf_size); in qmc_chan_set_param()
374 return -EINVAL; in qmc_chan_set_param()
387 u16 ctrl; in qmc_chan_write_submit() local
398 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_write_submit()
399 bd = chan->txbd_free; in qmc_chan_write_submit()
401 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_write_submit()
402 if (ctrl & (QMC_BD_TX_R | QMC_BD_TX_UB)) { in qmc_chan_write_submit()
404 ret = -EBUSY; in qmc_chan_write_submit()
408 qmc_write16(&bd->cbd_datlen, length); in qmc_chan_write_submit()
409 qmc_write32(&bd->cbd_bufaddr, addr); in qmc_chan_write_submit()
411 xfer_desc = &chan->tx_desc[bd - chan->txbds]; in qmc_chan_write_submit()
412 xfer_desc->tx_complete = complete; in qmc_chan_write_submit()
413 xfer_desc->context = context; in qmc_chan_write_submit()
416 ctrl |= (QMC_BD_TX_R | QMC_BD_TX_UB); in qmc_chan_write_submit()
418 qmc_write16(&bd->cbd_sc, ctrl); in qmc_chan_write_submit()
420 if (!chan->is_tx_stopped) in qmc_chan_write_submit()
421 qmc_setbits16(chan->s_param + QMC_SPE_CHAMR, QMC_SPE_CHAMR_POL); in qmc_chan_write_submit()
423 if (ctrl & QMC_BD_TX_W) in qmc_chan_write_submit()
424 chan->txbd_free = chan->txbds; in qmc_chan_write_submit()
426 chan->txbd_free++; in qmc_chan_write_submit()
431 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_write_submit()
443 u16 ctrl; in qmc_chan_write_done() local
453 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_write_done()
454 bd = chan->txbd_done; in qmc_chan_write_done()
456 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_write_done()
457 while (!(ctrl & QMC_BD_TX_R)) { in qmc_chan_write_done()
458 if (!(ctrl & QMC_BD_TX_UB)) in qmc_chan_write_done()
461 xfer_desc = &chan->tx_desc[bd - chan->txbds]; in qmc_chan_write_done()
462 complete = xfer_desc->tx_complete; in qmc_chan_write_done()
463 context = xfer_desc->context; in qmc_chan_write_done()
464 xfer_desc->tx_complete = NULL; in qmc_chan_write_done()
465 xfer_desc->context = NULL; in qmc_chan_write_done()
467 qmc_write16(&bd->cbd_sc, ctrl & ~QMC_BD_TX_UB); in qmc_chan_write_done()
469 if (ctrl & QMC_BD_TX_W) in qmc_chan_write_done()
470 chan->txbd_done = chan->txbds; in qmc_chan_write_done()
472 chan->txbd_done++; in qmc_chan_write_done()
475 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_write_done()
477 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_write_done()
480 bd = chan->txbd_done; in qmc_chan_write_done()
481 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_write_done()
485 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_write_done()
495 u16 ctrl; in qmc_chan_read_submit() local
506 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_read_submit()
507 bd = chan->rxbd_free; in qmc_chan_read_submit()
509 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_read_submit()
510 if (ctrl & (QMC_BD_RX_E | QMC_BD_RX_UB)) { in qmc_chan_read_submit()
512 ret = -EBUSY; in qmc_chan_read_submit()
516 qmc_write16(&bd->cbd_datlen, 0); /* data length is updated by the QMC */ in qmc_chan_read_submit()
517 qmc_write32(&bd->cbd_bufaddr, addr); in qmc_chan_read_submit()
519 xfer_desc = &chan->rx_desc[bd - chan->rxbds]; in qmc_chan_read_submit()
520 xfer_desc->rx_complete = complete; in qmc_chan_read_submit()
521 xfer_desc->context = context; in qmc_chan_read_submit()
524 ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO | in qmc_chan_read_submit()
528 ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB); in qmc_chan_read_submit()
530 qmc_write16(&bd->cbd_sc, ctrl); in qmc_chan_read_submit()
533 if (chan->is_rx_halted && !chan->is_rx_stopped) { in qmc_chan_read_submit()
535 if (chan->mode == QMC_TRANSPARENT) in qmc_chan_read_submit()
536 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080); in qmc_chan_read_submit()
538 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x00000080); in qmc_chan_read_submit()
539 qmc_write32(chan->s_param + QMC_SPE_RSTATE, 0x31000000); in qmc_chan_read_submit()
540 chan->is_rx_halted = false; in qmc_chan_read_submit()
542 chan->rx_pending++; in qmc_chan_read_submit()
544 if (ctrl & QMC_BD_RX_W) in qmc_chan_read_submit()
545 chan->rxbd_free = chan->rxbds; in qmc_chan_read_submit()
547 chan->rxbd_free++; in qmc_chan_read_submit()
551 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_read_submit()
564 u16 ctrl; in qmc_chan_read_done() local
574 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_read_done()
575 bd = chan->rxbd_done; in qmc_chan_read_done()
577 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_read_done()
578 while (!(ctrl & QMC_BD_RX_E)) { in qmc_chan_read_done()
579 if (!(ctrl & QMC_BD_RX_UB)) in qmc_chan_read_done()
582 xfer_desc = &chan->rx_desc[bd - chan->rxbds]; in qmc_chan_read_done()
583 complete = xfer_desc->rx_complete; in qmc_chan_read_done()
584 context = xfer_desc->context; in qmc_chan_read_done()
585 xfer_desc->rx_complete = NULL; in qmc_chan_read_done()
586 xfer_desc->context = NULL; in qmc_chan_read_done()
588 datalen = qmc_read16(&bd->cbd_datlen); in qmc_chan_read_done()
589 qmc_write16(&bd->cbd_sc, ctrl & ~QMC_BD_RX_UB); in qmc_chan_read_done()
591 if (ctrl & QMC_BD_RX_W) in qmc_chan_read_done()
592 chan->rxbd_done = chan->rxbds; in qmc_chan_read_done()
594 chan->rxbd_done++; in qmc_chan_read_done()
596 chan->rx_pending--; in qmc_chan_read_done()
599 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_read_done()
604 * -> Be sure that the software API flags are consistent in qmc_chan_read_done()
615 ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | in qmc_chan_read_done()
617 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_read_done()
620 bd = chan->rxbd_done; in qmc_chan_read_done()
621 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_read_done()
625 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_read_done()
636 * Use a common Tx/Rx 64 entries table. in qmc_chan_setup_tsa_64rxtx()
637 * Tx and Rx related stuffs must be identical in qmc_chan_setup_tsa_64rxtx()
639 if (chan->tx_ts_mask != chan->rx_ts_mask) { in qmc_chan_setup_tsa_64rxtx()
640 dev_err(chan->qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id); in qmc_chan_setup_tsa_64rxtx()
641 return -EINVAL; in qmc_chan_setup_tsa_64rxtx()
644 val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); in qmc_chan_setup_tsa_64rxtx()
646 /* Check entries based on Rx stuff*/ in qmc_chan_setup_tsa_64rxtx()
647 for (i = 0; i < info->nb_rx_ts; i++) { in qmc_chan_setup_tsa_64rxtx()
648 if (!(chan->rx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_64rxtx()
651 curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); in qmc_chan_setup_tsa_64rxtx()
653 dev_err(chan->qmc->dev, "chan %u TxRx entry %d already used\n", in qmc_chan_setup_tsa_64rxtx()
654 chan->id, i); in qmc_chan_setup_tsa_64rxtx()
655 return -EBUSY; in qmc_chan_setup_tsa_64rxtx()
659 /* Set entries based on Rx stuff*/ in qmc_chan_setup_tsa_64rxtx()
660 for (i = 0; i < info->nb_rx_ts; i++) { in qmc_chan_setup_tsa_64rxtx()
661 if (!(chan->rx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_64rxtx()
664 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), in qmc_chan_setup_tsa_64rxtx()
678 /* Use a Rx 32 entries table */ in qmc_chan_setup_tsa_32rx()
680 val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); in qmc_chan_setup_tsa_32rx()
682 /* Check entries based on Rx stuff */ in qmc_chan_setup_tsa_32rx()
683 for (i = 0; i < info->nb_rx_ts; i++) { in qmc_chan_setup_tsa_32rx()
684 if (!(chan->rx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_32rx()
687 curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); in qmc_chan_setup_tsa_32rx()
689 dev_err(chan->qmc->dev, "chan %u Rx entry %d already used\n", in qmc_chan_setup_tsa_32rx()
690 chan->id, i); in qmc_chan_setup_tsa_32rx()
691 return -EBUSY; in qmc_chan_setup_tsa_32rx()
695 /* Set entries based on Rx stuff */ in qmc_chan_setup_tsa_32rx()
696 for (i = 0; i < info->nb_rx_ts; i++) { in qmc_chan_setup_tsa_32rx()
697 if (!(chan->rx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_32rx()
700 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), in qmc_chan_setup_tsa_32rx()
716 val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); in qmc_chan_setup_tsa_32tx()
719 for (i = 0; i < info->nb_tx_ts; i++) { in qmc_chan_setup_tsa_32tx()
720 if (!(chan->tx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_32tx()
723 curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2)); in qmc_chan_setup_tsa_32tx()
725 dev_err(chan->qmc->dev, "chan %u Tx entry %d already used\n", in qmc_chan_setup_tsa_32tx()
726 chan->id, i); in qmc_chan_setup_tsa_32tx()
727 return -EBUSY; in qmc_chan_setup_tsa_32tx()
732 for (i = 0; i < info->nb_tx_ts; i++) { in qmc_chan_setup_tsa_32tx()
733 if (!(chan->tx_ts_mask & (((u64)1) << i))) in qmc_chan_setup_tsa_32tx()
736 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), in qmc_chan_setup_tsa_32tx()
749 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); in qmc_chan_setup_tsa_tx()
754 if (chan->qmc->is_tsa_64rxtx) in qmc_chan_setup_tsa_tx()
766 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); in qmc_chan_setup_tsa_rx()
771 if (chan->qmc->is_tsa_64rxtx) in qmc_chan_setup_tsa_rx()
779 return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E); in qmc_chan_command()
787 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_stop_rx()
789 if (chan->is_rx_stopped) { in qmc_chan_stop_rx()
790 /* The channel is already stopped -> simply return ok */ in qmc_chan_stop_rx()
798 dev_err(chan->qmc->dev, "chan %u: Send STOP RECEIVE failed (%d)\n", in qmc_chan_stop_rx()
799 chan->id, ret); in qmc_chan_stop_rx()
803 chan->is_rx_stopped = true; in qmc_chan_stop_rx()
805 if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) { in qmc_chan_stop_rx()
808 dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", in qmc_chan_stop_rx()
809 chan->id, ret); in qmc_chan_stop_rx()
815 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_stop_rx()
824 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_stop_tx()
826 if (chan->is_tx_stopped) { in qmc_chan_stop_tx()
827 /* The channel is already stopped -> simply return ok */ in qmc_chan_stop_tx()
835 dev_err(chan->qmc->dev, "chan %u: Send STOP TRANSMIT failed (%d)\n", in qmc_chan_stop_tx()
836 chan->id, ret); in qmc_chan_stop_tx()
840 chan->is_tx_stopped = true; in qmc_chan_stop_tx()
842 if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) { in qmc_chan_stop_tx()
845 dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", in qmc_chan_stop_tx()
846 chan->id, ret); in qmc_chan_stop_tx()
852 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_stop_tx()
864 spin_lock_irqsave(&chan->ts_lock, flags); in qmc_chan_stop()
867 is_rx_rollback_needed = !chan->is_rx_stopped; in qmc_chan_stop()
876 /* Restart rx if needed */ in qmc_chan_stop()
884 spin_unlock_irqrestore(&chan->ts_lock, flags); in qmc_chan_stop()
897 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info); in qmc_setup_chan_trnsync()
901 /* Find the first Rx TS allocated to the channel */ in qmc_setup_chan_trnsync()
902 first_rx = chan->rx_ts_mask ? __ffs64(chan->rx_ts_mask) + 1 : 0; in qmc_setup_chan_trnsync()
905 last_tx = fls64(chan->tx_ts_mask); in qmc_setup_chan_trnsync()
913 qmc_write16(chan->s_param + QMC_SPE_TRNSYNC, trnsync); in qmc_setup_chan_trnsync()
915 dev_dbg(qmc->dev, "chan %u: trnsync=0x%04x, rx %u/%u 0x%llx, tx %u/%u 0x%llx\n", in qmc_setup_chan_trnsync()
916 chan->id, trnsync, in qmc_setup_chan_trnsync()
917 first_rx, info.nb_rx_ts, chan->rx_ts_mask, in qmc_setup_chan_trnsync()
918 last_tx, info.nb_tx_ts, chan->tx_ts_mask); in qmc_setup_chan_trnsync()
928 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_start_rx()
930 if (!chan->is_rx_stopped) { in qmc_chan_start_rx()
931 /* The channel is already started -> simply return ok */ in qmc_chan_start_rx()
938 dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", in qmc_chan_start_rx()
939 chan->id, ret); in qmc_chan_start_rx()
943 ret = qmc_setup_chan_trnsync(chan->qmc, chan); in qmc_chan_start_rx()
945 dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", in qmc_chan_start_rx()
946 chan->id, ret); in qmc_chan_start_rx()
951 if (chan->mode == QMC_TRANSPARENT) in qmc_chan_start_rx()
952 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080); in qmc_chan_start_rx()
954 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x00000080); in qmc_chan_start_rx()
955 qmc_write32(chan->s_param + QMC_SPE_RSTATE, 0x31000000); in qmc_chan_start_rx()
956 chan->is_rx_halted = false; in qmc_chan_start_rx()
958 chan->is_rx_stopped = false; in qmc_chan_start_rx()
961 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_start_rx()
970 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_start_tx()
972 if (!chan->is_tx_stopped) { in qmc_chan_start_tx()
973 /* The channel is already started -> simply return ok */ in qmc_chan_start_tx()
980 dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", in qmc_chan_start_tx()
981 chan->id, ret); in qmc_chan_start_tx()
985 ret = qmc_setup_chan_trnsync(chan->qmc, chan); in qmc_chan_start_tx()
987 dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", in qmc_chan_start_tx()
988 chan->id, ret); in qmc_chan_start_tx()
996 qmc_setbits16(chan->s_param + QMC_SPE_CHAMR, QMC_SPE_CHAMR_ENT); in qmc_chan_start_tx()
999 qmc_setbits16(chan->s_param + QMC_SPE_CHAMR, QMC_SPE_CHAMR_POL); in qmc_chan_start_tx()
1001 chan->is_tx_stopped = false; in qmc_chan_start_tx()
1004 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_start_tx()
1014 spin_lock_irqsave(&chan->ts_lock, flags); in qmc_chan_start()
1017 is_rx_rollback_needed = chan->is_rx_stopped; in qmc_chan_start()
1026 /* Restop rx if needed */ in qmc_chan_start()
1034 spin_unlock_irqrestore(&chan->ts_lock, flags); in qmc_chan_start()
1044 u16 ctrl; in qmc_chan_reset_rx() local
1046 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_chan_reset_rx()
1047 bd = chan->rxbds; in qmc_chan_reset_rx()
1049 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_reset_rx()
1050 qmc_write16(&bd->cbd_sc, ctrl & ~(QMC_BD_RX_UB | QMC_BD_RX_E)); in qmc_chan_reset_rx()
1052 xfer_desc = &chan->rx_desc[bd - chan->rxbds]; in qmc_chan_reset_rx()
1053 xfer_desc->rx_complete = NULL; in qmc_chan_reset_rx()
1054 xfer_desc->context = NULL; in qmc_chan_reset_rx()
1057 } while (!(ctrl & QMC_BD_RX_W)); in qmc_chan_reset_rx()
1059 chan->rxbd_free = chan->rxbds; in qmc_chan_reset_rx()
1060 chan->rxbd_done = chan->rxbds; in qmc_chan_reset_rx()
1061 qmc_write16(chan->s_param + QMC_SPE_RBPTR, in qmc_chan_reset_rx()
1062 qmc_read16(chan->s_param + QMC_SPE_RBASE)); in qmc_chan_reset_rx()
1064 chan->rx_pending = 0; in qmc_chan_reset_rx()
1066 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_chan_reset_rx()
1074 u16 ctrl; in qmc_chan_reset_tx() local
1076 spin_lock_irqsave(&chan->tx_lock, flags); in qmc_chan_reset_tx()
1078 /* Disable transmitter. It will be re-enable on qmc_chan_start() */ in qmc_chan_reset_tx()
1079 qmc_clrbits16(chan->s_param + QMC_SPE_CHAMR, QMC_SPE_CHAMR_ENT); in qmc_chan_reset_tx()
1081 bd = chan->txbds; in qmc_chan_reset_tx()
1083 ctrl = qmc_read16(&bd->cbd_sc); in qmc_chan_reset_tx()
1084 qmc_write16(&bd->cbd_sc, ctrl & ~(QMC_BD_TX_UB | QMC_BD_TX_R)); in qmc_chan_reset_tx()
1086 xfer_desc = &chan->tx_desc[bd - chan->txbds]; in qmc_chan_reset_tx()
1087 xfer_desc->tx_complete = NULL; in qmc_chan_reset_tx()
1088 xfer_desc->context = NULL; in qmc_chan_reset_tx()
1091 } while (!(ctrl & QMC_BD_TX_W)); in qmc_chan_reset_tx()
1093 chan->txbd_free = chan->txbds; in qmc_chan_reset_tx()
1094 chan->txbd_done = chan->txbds; in qmc_chan_reset_tx()
1095 qmc_write16(chan->s_param + QMC_SPE_TBPTR, in qmc_chan_reset_tx()
1096 qmc_read16(chan->s_param + QMC_SPE_TBASE)); in qmc_chan_reset_tx()
1099 qmc_write32(chan->s_param + QMC_SPE_TSTATE, 0x30000000); in qmc_chan_reset_tx()
1100 qmc_write32(chan->s_param + QMC_SPE_ZISTATE, 0x00000100); in qmc_chan_reset_tx()
1102 spin_unlock_irqrestore(&chan->tx_lock, flags); in qmc_chan_reset_tx()
1126 ret = tsa_serial_get_info(qmc->tsa_serial, &info); in qmc_check_chans()
1131 dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned not supported\n"); in qmc_check_chans()
1132 return -EINVAL; in qmc_check_chans()
1137 * used for Tx and Rx and so masks must be equal for all channels. in qmc_check_chans()
1141 dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned are not equal\n"); in qmc_check_chans()
1142 return -EINVAL; in qmc_check_chans()
1146 tx_ts_assigned_mask = info.nb_tx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_tx_ts) - 1; in qmc_check_chans()
1147 rx_ts_assigned_mask = info.nb_rx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_rx_ts) - 1; in qmc_check_chans()
1149 list_for_each_entry(chan, &qmc->chan_head, list) { in qmc_check_chans()
1150 if (chan->tx_ts_mask_avail > tx_ts_assigned_mask) { in qmc_check_chans()
1151 dev_err(qmc->dev, "chan %u can use TSA unassigned Tx TS\n", chan->id); in qmc_check_chans()
1152 return -EINVAL; in qmc_check_chans()
1155 if (chan->rx_ts_mask_avail > rx_ts_assigned_mask) { in qmc_check_chans()
1156 dev_err(qmc->dev, "chan %u can use TSA unassigned Rx TS\n", chan->id); in qmc_check_chans()
1157 return -EINVAL; in qmc_check_chans()
1169 list_for_each_entry(chan, &qmc->chan_head, list) in qmc_nb_chans()
1187 dev_err(qmc->dev, "%pOF: failed to read reg\n", chan_np); in qmc_of_parse_chans()
1192 dev_err(qmc->dev, "%pOF: Invalid chan_id\n", chan_np); in qmc_of_parse_chans()
1194 return -EINVAL; in qmc_of_parse_chans()
1197 chan = devm_kzalloc(qmc->dev, sizeof(*chan), GFP_KERNEL); in qmc_of_parse_chans()
1200 return -ENOMEM; in qmc_of_parse_chans()
1203 chan->id = chan_id; in qmc_of_parse_chans()
1204 spin_lock_init(&chan->ts_lock); in qmc_of_parse_chans()
1205 spin_lock_init(&chan->rx_lock); in qmc_of_parse_chans()
1206 spin_lock_init(&chan->tx_lock); in qmc_of_parse_chans()
1208 ret = of_property_read_u64(chan_np, "fsl,tx-ts-mask", &ts_mask); in qmc_of_parse_chans()
1210 dev_err(qmc->dev, "%pOF: failed to read fsl,tx-ts-mask\n", in qmc_of_parse_chans()
1215 chan->tx_ts_mask_avail = ts_mask; in qmc_of_parse_chans()
1216 chan->tx_ts_mask = chan->tx_ts_mask_avail; in qmc_of_parse_chans()
1218 ret = of_property_read_u64(chan_np, "fsl,rx-ts-mask", &ts_mask); in qmc_of_parse_chans()
1220 dev_err(qmc->dev, "%pOF: failed to read fsl,rx-ts-mask\n", in qmc_of_parse_chans()
1225 chan->rx_ts_mask_avail = ts_mask; in qmc_of_parse_chans()
1226 chan->rx_ts_mask = chan->rx_ts_mask_avail; in qmc_of_parse_chans()
1229 ret = of_property_read_string(chan_np, "fsl,operational-mode", &mode); in qmc_of_parse_chans()
1230 if (ret && ret != -EINVAL) { in qmc_of_parse_chans()
1231 dev_err(qmc->dev, "%pOF: failed to read fsl,operational-mode\n", in qmc_of_parse_chans()
1237 chan->mode = QMC_TRANSPARENT; in qmc_of_parse_chans()
1239 chan->mode = QMC_HDLC; in qmc_of_parse_chans()
1241 dev_err(qmc->dev, "%pOF: Invalid fsl,operational-mode (%s)\n", in qmc_of_parse_chans()
1244 return -EINVAL; in qmc_of_parse_chans()
1247 chan->is_reverse_data = of_property_read_bool(chan_np, in qmc_of_parse_chans()
1248 "fsl,reverse-data"); in qmc_of_parse_chans()
1250 list_add_tail(&chan->list, &qmc->chan_head); in qmc_of_parse_chans()
1251 qmc->chans[chan->id] = chan; in qmc_of_parse_chans()
1263 * Use a common Tx/Rx 64 entries table. in qmc_init_tsa_64rxtx()
1264 * Everything was previously checked, Tx and Rx related stuffs are in qmc_init_tsa_64rxtx()
1265 * identical -> Used Rx related stuff to build the table in qmc_init_tsa_64rxtx()
1267 qmc->is_tsa_64rxtx = true; in qmc_init_tsa_64rxtx()
1271 qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000); in qmc_init_tsa_64rxtx()
1274 qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2), in qmc_init_tsa_64rxtx()
1278 val = qmc->scc_pram_offset + QMC_GBL_TSATRX; in qmc_init_tsa_64rxtx()
1279 qmc_write16(qmc->scc_pram + QMC_GBL_RX_S_PTR, val); in qmc_init_tsa_64rxtx()
1280 qmc_write16(qmc->scc_pram + QMC_GBL_RXPTR, val); in qmc_init_tsa_64rxtx()
1281 qmc_write16(qmc->scc_pram + QMC_GBL_TX_S_PTR, val); in qmc_init_tsa_64rxtx()
1282 qmc_write16(qmc->scc_pram + QMC_GBL_TXPTR, val); in qmc_init_tsa_64rxtx()
1293 * Use a Tx 32 entries table and a Rx 32 entries table. in qmc_init_tsa_32rx_32tx()
1296 qmc->is_tsa_64rxtx = false; in qmc_init_tsa_32rx_32tx()
1300 qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000); in qmc_init_tsa_32rx_32tx()
1301 qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 0x0000); in qmc_init_tsa_32rx_32tx()
1305 qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2), in qmc_init_tsa_32rx_32tx()
1307 qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATTX + ((info->nb_tx_ts - 1) * 2), in qmc_init_tsa_32rx_32tx()
1310 /* Init Rx pointers ...*/ in qmc_init_tsa_32rx_32tx()
1311 val = qmc->scc_pram_offset + QMC_GBL_TSATRX; in qmc_init_tsa_32rx_32tx()
1312 qmc_write16(qmc->scc_pram + QMC_GBL_RX_S_PTR, val); in qmc_init_tsa_32rx_32tx()
1313 qmc_write16(qmc->scc_pram + QMC_GBL_RXPTR, val); in qmc_init_tsa_32rx_32tx()
1316 val = qmc->scc_pram_offset + QMC_GBL_TSATTX; in qmc_init_tsa_32rx_32tx()
1317 qmc_write16(qmc->scc_pram + QMC_GBL_TX_S_PTR, val); in qmc_init_tsa_32rx_32tx()
1318 qmc_write16(qmc->scc_pram + QMC_GBL_TXPTR, val); in qmc_init_tsa_32rx_32tx()
1329 ret = tsa_serial_get_info(qmc->tsa_serial, &info); in qmc_init_tsa()
1349 chan->qmc = qmc; in qmc_setup_chan()
1352 chan->s_param = qmc->dpram + (chan->id * 64); in qmc_setup_chan()
1353 /* 16 bd per channel (8 rx and 8 tx) */ in qmc_setup_chan()
1354 chan->txbds = qmc->bd_table + (chan->id * (QMC_NB_TXBDS + QMC_NB_RXBDS)); in qmc_setup_chan()
1355 chan->rxbds = qmc->bd_table + (chan->id * (QMC_NB_TXBDS + QMC_NB_RXBDS)) + QMC_NB_TXBDS; in qmc_setup_chan()
1357 chan->txbd_free = chan->txbds; in qmc_setup_chan()
1358 chan->txbd_done = chan->txbds; in qmc_setup_chan()
1359 chan->rxbd_free = chan->rxbds; in qmc_setup_chan()
1360 chan->rxbd_done = chan->rxbds; in qmc_setup_chan()
1363 val = chan->id * (QMC_NB_TXBDS + QMC_NB_RXBDS) * sizeof(cbd_t); in qmc_setup_chan()
1364 qmc_write16(chan->s_param + QMC_SPE_TBASE, val); in qmc_setup_chan()
1365 qmc_write16(chan->s_param + QMC_SPE_TBPTR, val); in qmc_setup_chan()
1368 val = ((chan->id * (QMC_NB_TXBDS + QMC_NB_RXBDS)) + QMC_NB_TXBDS) * sizeof(cbd_t); in qmc_setup_chan()
1369 qmc_write16(chan->s_param + QMC_SPE_RBASE, val); in qmc_setup_chan()
1370 qmc_write16(chan->s_param + QMC_SPE_RBPTR, val); in qmc_setup_chan()
1371 qmc_write32(chan->s_param + QMC_SPE_TSTATE, 0x30000000); in qmc_setup_chan()
1372 qmc_write32(chan->s_param + QMC_SPE_RSTATE, 0x31000000); in qmc_setup_chan()
1373 qmc_write32(chan->s_param + QMC_SPE_ZISTATE, 0x00000100); in qmc_setup_chan()
1374 if (chan->mode == QMC_TRANSPARENT) { in qmc_setup_chan()
1375 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080); in qmc_setup_chan()
1376 qmc_write16(chan->s_param + QMC_SPE_TMRBLR, 60); in qmc_setup_chan()
1378 if (chan->is_reverse_data) in qmc_setup_chan()
1380 qmc_write16(chan->s_param + QMC_SPE_CHAMR, val); in qmc_setup_chan()
1385 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x00000080); in qmc_setup_chan()
1386 qmc_write16(chan->s_param + QMC_SPE_MFLR, 60); in qmc_setup_chan()
1387 qmc_write16(chan->s_param + QMC_SPE_CHAMR, in qmc_setup_chan()
1392 qmc_write16(chan->s_param + QMC_SPE_INTMSK, 0x0000); in qmc_setup_chan()
1394 /* Init Rx BDs and set Wrap bit on last descriptor */ in qmc_setup_chan()
1398 bd = chan->rxbds + i; in qmc_setup_chan()
1399 qmc_write16(&bd->cbd_sc, val); in qmc_setup_chan()
1401 bd = chan->rxbds + QMC_NB_RXBDS - 1; in qmc_setup_chan()
1402 qmc_write16(&bd->cbd_sc, val | QMC_BD_RX_W); in qmc_setup_chan()
1407 if (chan->mode == QMC_HDLC) in qmc_setup_chan()
1410 bd = chan->txbds + i; in qmc_setup_chan()
1411 qmc_write16(&bd->cbd_sc, val); in qmc_setup_chan()
1413 bd = chan->txbds + QMC_NB_TXBDS - 1; in qmc_setup_chan()
1414 qmc_write16(&bd->cbd_sc, val | QMC_BD_TX_W); in qmc_setup_chan()
1424 list_for_each_entry(chan, &qmc->chan_head, list) { in qmc_setup_chans()
1438 list_for_each_entry(chan, &qmc->chan_head, list) { in qmc_finalize_chans()
1440 if (chan->mode == QMC_HDLC) { in qmc_finalize_chans()
1441 qmc_write16(chan->s_param + QMC_SPE_INTMSK, in qmc_finalize_chans()
1446 qmc_write16(chan->s_param + QMC_SPE_INTMSK, in qmc_finalize_chans()
1466 for (i = 0; i < (qmc->int_size / sizeof(u16)); i++) in qmc_setup_ints()
1467 qmc_write16(qmc->int_table + i, 0x0000); in qmc_setup_ints()
1470 if (qmc->int_size >= sizeof(u16)) { in qmc_setup_ints()
1471 last = qmc->int_table + (qmc->int_size / sizeof(u16)) - 1; in qmc_setup_ints()
1485 int_entry = qmc_read16(qmc->int_curr); in qmc_irq_gint()
1488 qmc_write16(qmc->int_curr, int_entry & QMC_INT_W); in qmc_irq_gint()
1491 chan = qmc->chans[chan_id]; in qmc_irq_gint()
1493 dev_err(qmc->dev, "interrupt on invalid chan %u\n", chan_id); in qmc_irq_gint()
1501 dev_info(qmc->dev, "intr chan %u, 0x%04x (UN)\n", chan_id, in qmc_irq_gint()
1503 chan->nb_tx_underrun++; in qmc_irq_gint()
1507 dev_info(qmc->dev, "intr chan %u, 0x%04x (BSY)\n", chan_id, in qmc_irq_gint()
1509 chan->nb_rx_busy++; in qmc_irq_gint()
1511 spin_lock_irqsave(&chan->rx_lock, flags); in qmc_irq_gint()
1512 if (chan->rx_pending && !chan->is_rx_stopped) { in qmc_irq_gint()
1513 if (chan->mode == QMC_TRANSPARENT) in qmc_irq_gint()
1514 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080); in qmc_irq_gint()
1516 qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x00000080); in qmc_irq_gint()
1517 qmc_write32(chan->s_param + QMC_SPE_RSTATE, 0x31000000); in qmc_irq_gint()
1518 chan->is_rx_halted = false; in qmc_irq_gint()
1520 chan->is_rx_halted = true; in qmc_irq_gint()
1522 spin_unlock_irqrestore(&chan->rx_lock, flags); in qmc_irq_gint()
1530 qmc->int_curr = qmc->int_table; in qmc_irq_gint()
1532 qmc->int_curr++; in qmc_irq_gint()
1533 int_entry = qmc_read16(qmc->int_curr); in qmc_irq_gint()
1542 scce = qmc_read16(qmc->scc_regs + SCC_SCCE); in qmc_irq_handler()
1543 qmc_write16(qmc->scc_regs + SCC_SCCE, scce); in qmc_irq_handler()
1546 dev_info(qmc->dev, "IRQ queue overflow\n"); in qmc_irq_handler()
1549 dev_err(qmc->dev, "Global transmitter underrun\n"); in qmc_irq_handler()
1552 dev_err(qmc->dev, "Global receiver overrun\n"); in qmc_irq_handler()
1563 struct device_node *np = pdev->dev.of_node; in qmc_probe()
1570 qmc = devm_kzalloc(&pdev->dev, sizeof(*qmc), GFP_KERNEL); in qmc_probe()
1572 return -ENOMEM; in qmc_probe()
1574 qmc->dev = &pdev->dev; in qmc_probe()
1575 INIT_LIST_HEAD(&qmc->chan_head); in qmc_probe()
1577 qmc->scc_regs = devm_platform_ioremap_resource_byname(pdev, "scc_regs"); in qmc_probe()
1578 if (IS_ERR(qmc->scc_regs)) in qmc_probe()
1579 return PTR_ERR(qmc->scc_regs); in qmc_probe()
1584 return -EINVAL; in qmc_probe()
1585 qmc->scc_pram_offset = res->start - get_immrbase(); in qmc_probe()
1586 qmc->scc_pram = devm_ioremap_resource(qmc->dev, res); in qmc_probe()
1587 if (IS_ERR(qmc->scc_pram)) in qmc_probe()
1588 return PTR_ERR(qmc->scc_pram); in qmc_probe()
1590 qmc->dpram = devm_platform_ioremap_resource_byname(pdev, "dpram"); in qmc_probe()
1591 if (IS_ERR(qmc->dpram)) in qmc_probe()
1592 return PTR_ERR(qmc->dpram); in qmc_probe()
1594 qmc->tsa_serial = devm_tsa_serial_get_byphandle(qmc->dev, np, "fsl,tsa-serial"); in qmc_probe()
1595 if (IS_ERR(qmc->tsa_serial)) { in qmc_probe()
1596 return dev_err_probe(qmc->dev, PTR_ERR(qmc->tsa_serial), in qmc_probe()
1601 ret = tsa_serial_connect(qmc->tsa_serial); in qmc_probe()
1603 dev_err(qmc->dev, "Failed to connect TSA serial\n"); in qmc_probe()
1615 qmc_write32(qmc->scc_regs + SCC_GSMRH, in qmc_probe()
1619 qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC); in qmc_probe()
1623 * 8 rx and 8 tx descriptors per channel in qmc_probe()
1625 qmc->bd_size = (nb_chans * (QMC_NB_TXBDS + QMC_NB_RXBDS)) * sizeof(cbd_t); in qmc_probe()
1626 qmc->bd_table = dmam_alloc_coherent(qmc->dev, qmc->bd_size, in qmc_probe()
1627 &qmc->bd_dma_addr, GFP_KERNEL); in qmc_probe()
1628 if (!qmc->bd_table) { in qmc_probe()
1629 dev_err(qmc->dev, "Failed to allocate bd table\n"); in qmc_probe()
1630 ret = -ENOMEM; in qmc_probe()
1633 memset(qmc->bd_table, 0, qmc->bd_size); in qmc_probe()
1635 qmc_write32(qmc->scc_pram + QMC_GBL_MCBASE, qmc->bd_dma_addr); in qmc_probe()
1638 qmc->int_size = QMC_NB_INTS * sizeof(u16); in qmc_probe()
1639 qmc->int_table = dmam_alloc_coherent(qmc->dev, qmc->int_size, in qmc_probe()
1640 &qmc->int_dma_addr, GFP_KERNEL); in qmc_probe()
1641 if (!qmc->int_table) { in qmc_probe()
1642 dev_err(qmc->dev, "Failed to allocate interrupt table\n"); in qmc_probe()
1643 ret = -ENOMEM; in qmc_probe()
1646 memset(qmc->int_table, 0, qmc->int_size); in qmc_probe()
1648 qmc->int_curr = qmc->int_table; in qmc_probe()
1649 qmc_write32(qmc->scc_pram + QMC_GBL_INTBASE, qmc->int_dma_addr); in qmc_probe()
1650 qmc_write32(qmc->scc_pram + QMC_GBL_INTPTR, qmc->int_dma_addr); in qmc_probe()
1653 qmc_write16(qmc->scc_pram + QMC_GBL_MRBLR, HDLC_MAX_MRU + 4); in qmc_probe()
1655 qmc_write16(qmc->scc_pram + QMC_GBL_GRFTHR, 1); in qmc_probe()
1656 qmc_write16(qmc->scc_pram + QMC_GBL_GRFCNT, 1); in qmc_probe()
1658 qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3); in qmc_probe()
1659 qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8); in qmc_probe()
1665 qmc_write16(qmc->scc_pram + QMC_GBL_QMCSTATE, 0x8000); in qmc_probe()
1677 qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000); in qmc_probe()
1678 qmc_write16(qmc->scc_regs + SCC_SCCE, 0x000F); in qmc_probe()
1682 ret = devm_request_irq(qmc->dev, irq, qmc_irq_handler, 0, "qmc", qmc); in qmc_probe()
1687 qmc_write16(qmc->scc_regs + SCC_SCCM, in qmc_probe()
1695 qmc_setbits32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_ENR | SCC_GSMRL_ENT); in qmc_probe()
1700 ret = devm_of_platform_populate(qmc->dev); in qmc_probe()
1707 qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0); in qmc_probe()
1710 qmc_write16(qmc->scc_regs + SCC_SCCM, 0); in qmc_probe()
1713 tsa_serial_disconnect(qmc->tsa_serial); in qmc_probe()
1722 qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0); in qmc_remove()
1725 qmc_write16(qmc->scc_regs + SCC_SCCM, 0); in qmc_remove()
1728 tsa_serial_disconnect(qmc->tsa_serial); in qmc_remove()
1732 { .compatible = "fsl,cpm1-scc-qmc" },
1739 .name = "fsl-qmc",
1754 return ERR_PTR(-EINVAL); in qmc_chan_get_from_qmc()
1758 return ERR_PTR(-ENODEV); in qmc_chan_get_from_qmc()
1763 return ERR_PTR(-EPROBE_DEFER); in qmc_chan_get_from_qmc()
1766 if (chan_index >= ARRAY_SIZE(qmc->chans)) { in qmc_chan_get_from_qmc()
1768 return ERR_PTR(-EINVAL); in qmc_chan_get_from_qmc()
1771 qmc_chan = qmc->chans[chan_index]; in qmc_chan_get_from_qmc()
1774 return ERR_PTR(-ENOENT); in qmc_chan_get_from_qmc()
1793 return ERR_PTR(-EINVAL); in qmc_chan_get_byphandle()
1808 qmc_np = np->parent; in qmc_chan_get_bychild()
1811 return ERR_PTR(-EINVAL); in qmc_chan_get_bychild()
1819 put_device(chan->qmc->dev); in qmc_chan_put()
1839 return ERR_PTR(-ENOMEM); in devm_qmc_chan_get_byphandle()
1861 return ERR_PTR(-ENOMEM); in devm_qmc_chan_get_bychild()