Lines Matching +full:0 +full:x0000000f
36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
79 #define lpfc_sli_intf_valid_MASK 0x00000007
83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
93 #define lpfc_sli_intf_if_type_MASK 0x0000000F
95 #define LPFC_SLI_INTF_IF_TYPE_0 0
100 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
102 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
103 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
104 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
105 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
106 #define LPFC_SLI_INTF_FAMILY_G6 0xc
107 #define LPFC_SLI_INTF_FAMILY_G7 0xd
108 #define LPFC_SLI_INTF_FAMILY_G7P 0xe
110 #define lpfc_sli_intf_slirev_MASK 0x0000000F
114 #define lpfc_sli_intf_func_type_SHIFT 0
115 #define lpfc_sli_intf_func_type_MASK 0x00000001
117 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
134 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
144 #define LPFC_MBX_ERROR_RANGE 0x4000
145 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
146 #define LPFC_BMBX_BIT1_ADDR_LO 0
149 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
151 #define LPFC_ENTIRE_FCF_DATABASE 0
152 #define LPFC_DFLT_FCF_INDEX 0
155 #define LPFC_VF0 0
189 #define LPFC_PCI_FUNC0 0
196 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
197 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
198 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
199 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
200 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
201 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
202 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
203 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
204 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
212 #define LPFC_FCP_SCHED_BY_HDWQ 0
216 #define LPFC_NS_QUERY_GID_FT 0
226 #define LPFC_DEF_IMAX 0
234 #define LPFC_MIN_CPU_MAP 0
242 ULP_BDE64_SIZE_MASK = 0xffffff,
245 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT),
248 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT),
250 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT),
252 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT),
254 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT),
256 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT),
258 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT),
260 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT),
264 __le32 type_size; /* type 31:24, size 23:0 */
274 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
279 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
282 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
283 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
284 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
285 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
286 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
287 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
288 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
300 #define lpfc_idx_rsrc_rdy_SHIFT 0
301 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
305 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
309 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
313 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
317 #define lpfc_ftr_ashdr_MASK 0x00000001
324 #define lpfc_abts_orig_SHIFT 0
325 #define lpfc_abts_orig_MASK 0x00000001
328 #define LPFC_ABTS_UNSOL_INT 0
330 #define lpfc_abts_rxid_SHIFT 0
331 #define lpfc_abts_rxid_MASK 0x0000FFFF
334 #define lpfc_abts_oxid_MASK 0x0000FFFF
337 #define lpfc_vndr_code_SHIFT 0
338 #define lpfc_vndr_code_MASK 0x000000FF
341 #define lpfc_rsn_expln_MASK 0x000000FF
344 #define lpfc_rsn_code_MASK 0x000000FF
355 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
358 #define lpfc_eqe_minor_code_MASK 0x00000FFF
361 #define lpfc_eqe_major_code_MASK 0x00000007
363 #define lpfc_eqe_valid_SHIFT 0
364 #define lpfc_eqe_valid_MASK 0x00000001
375 #define lpfc_cqe_valid_MASK 0x00000001
378 #define lpfc_cqe_code_MASK 0x000000FF
383 #define CQE_STATUS_SUCCESS 0x0
384 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
385 #define CQE_STATUS_REMOTE_STOP 0x2
386 #define CQE_STATUS_LOCAL_REJECT 0x3
387 #define CQE_STATUS_NPORT_RJT 0x4
388 #define CQE_STATUS_FABRIC_RJT 0x5
389 #define CQE_STATUS_NPORT_BSY 0x6
390 #define CQE_STATUS_FABRIC_BSY 0x7
391 #define CQE_STATUS_INTERMED_RSP 0x8
392 #define CQE_STATUS_LS_RJT 0x9
393 #define CQE_STATUS_CMD_REJECT 0xb
394 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
395 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
396 #define CQE_STATUS_DI_ERROR 0x16
399 #define CQE_HW_STATUS_NO_ERR 0x0
400 #define CQE_HW_STATUS_UNDERRUN 0x1
401 #define CQE_HW_STATUS_OVERRUN 0x2
404 #define CQE_CODE_COMPL_WQE 0x1
405 #define CQE_CODE_RELEASE_WQE 0x2
406 #define CQE_CODE_RECEIVE 0x4
407 #define CQE_CODE_XRI_ABORTED 0x5
408 #define CQE_CODE_RECEIVE_V1 0x9
409 #define CQE_CODE_NVME_ERSP 0xd
413 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
415 #define WCQE_PARAM_MASK 0x1FF
421 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
424 #define lpfc_wcqe_c_status_MASK 0x000000FF
426 #define lpfc_wcqe_c_hw_status_SHIFT 0
427 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
429 #define lpfc_wcqe_c_ersp0_SHIFT 0
430 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
434 #define lpfc_wcqe_c_cmf_cg_MASK 0x00000001
436 #define lpfc_wcqe_c_cmf_bw_SHIFT 0
437 #define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF
441 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
444 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
447 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
450 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
452 #define lpfc_wcqe_c_bg_ge_SHIFT 0
453 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
460 #define lpfc_wcqe_c_xb_MASK 0x00000001
463 #define lpfc_wcqe_c_pv_MASK 0x00000001
466 #define lpfc_wcqe_c_priority_MASK 0x00000007
471 #define lpfc_wcqe_c_sqhead_SHIFT 0
472 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
482 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
484 #define lpfc_wcqe_r_wqe_index_SHIFT 0
485 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
499 #define lpfc_wcqe_xa_status_MASK 0x000000FF
504 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
506 #define lpfc_wcqe_xa_xri_SHIFT 0
507 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
514 #define lpfc_wcqe_xa_ia_MASK 0x00000001
516 #define CQE_XRI_ABORTED_IA_REMOTE 0
519 #define lpfc_wcqe_xa_br_MASK 0x00000001
521 #define CQE_XRI_ABORTED_BR_BA_ACC 0
524 #define lpfc_wcqe_xa_eo_MASK 0x00000001
526 #define CQE_XRI_ABORTED_EO_REMOTE 0
537 #define lpfc_rcqe_iv_MASK 0x00000001
540 #define lpfc_rcqe_status_MASK 0x000000FF
542 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
543 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
544 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
545 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
546 #define FC_STATUS_RQ_DMA_FAILURE 0x14 /* DMA failure */
548 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
549 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
553 #define lpfc_rcqe_length_MASK 0x0000FFFF
556 #define lpfc_rcqe_rq_id_MASK 0x000003FF
558 #define lpfc_rcqe_fcf_id_SHIFT 0
559 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
561 #define lpfc_rcqe_rq_id_v1_SHIFT 0
562 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
569 #define lpfc_rcqe_port_MASK 0x00000001
572 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
578 #define lpfc_rcqe_eof_MASK 0x000000FF
580 #define FCOE_EOFn 0x41
581 #define FCOE_EOFt 0x42
582 #define FCOE_EOFni 0x49
583 #define FCOE_EOFa 0x50
584 #define lpfc_rcqe_sof_SHIFT 0
585 #define lpfc_rcqe_sof_MASK 0x000000FF
587 #define FCOE_SOFi2 0x2d
588 #define FCOE_SOFi3 0x2e
589 #define FCOE_SOFn2 0x35
590 #define FCOE_SOFn3 0x36
604 #define lpfc_bde4_last_MASK 0x00000001
606 #define lpfc_bde4_sge_offset_SHIFT 0
607 #define lpfc_bde4_sge_offset_MASK 0x000003FF
610 #define lpfc_bde4_length_SHIFT 0
611 #define lpfc_bde4_length_MASK 0x000000FF
619 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
620 #define LPFC_PORT_SEM_MASK 0xF000
621 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
622 #define LPFC_UERR_STATUS_HI 0x00A4
623 #define LPFC_UERR_STATUS_LO 0x00A0
624 #define LPFC_UE_MASK_HI 0x00AC
625 #define LPFC_UE_MASK_LO 0x00A8
627 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
628 #define LPFC_SLI_INTF 0x0058
629 #define LPFC_SLI_ASIC_VER 0x009C
631 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
633 #define lpfc_port_smphr_perr_MASK 0x1
636 #define lpfc_port_smphr_sfi_MASK 0x1
639 #define lpfc_port_smphr_nip_MASK 0x1
642 #define lpfc_port_smphr_ipc_MASK 0x1
645 #define lpfc_port_smphr_scr1_MASK 0x1
648 #define lpfc_port_smphr_scr2_MASK 0x1
651 #define lpfc_port_smphr_host_scratch_MASK 0xFF
653 #define lpfc_port_smphr_port_status_SHIFT 0
654 #define lpfc_port_smphr_port_status_MASK 0xFFFF
657 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
658 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
659 #define LPFC_POST_STAGE_HOST_RDY 0x0002
660 #define LPFC_POST_STAGE_BE_RESET 0x0003
661 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
662 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
663 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
664 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
665 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
666 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
667 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
668 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
669 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
670 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
671 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
672 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
673 #define LPFC_POST_STAGE_ARMFW_START 0x0800
674 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
675 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
676 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
677 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
678 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
679 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
680 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
681 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
682 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
683 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
684 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
685 #define LPFC_POST_STAGE_RC_DONE 0x0B07
686 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
687 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
688 #define LPFC_POST_STAGE_PORT_READY 0xC000
689 #define LPFC_POST_STAGE_PORT_UE 0xF000
691 #define LPFC_CTL_PORT_STA_OFFSET 0x404
693 #define lpfc_sliport_status_err_MASK 0x1
696 #define lpfc_sliport_status_end_MASK 0x1
699 #define lpfc_sliport_status_oti_MASK 0x1
702 #define lpfc_sliport_status_dip_MASK 0x1
705 #define lpfc_sliport_status_rn_MASK 0x1
708 #define lpfc_sliport_status_rdy_MASK 0x1
710 #define lpfc_sliport_status_pldv_SHIFT 0
711 #define lpfc_sliport_status_pldv_MASK 0x1
713 #define CFG_PLD 0x3C
716 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
718 #define lpfc_sliport_ctrl_end_MASK 0x1
720 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
723 #define lpfc_sliport_ctrl_ip_MASK 0x1
727 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
728 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
730 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
732 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
734 #define lpfc_sliport_eqdelay_id_SHIFT 0
735 #define lpfc_sliport_eqdelay_id_MASK 0xfff
741 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
744 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
746 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
747 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
749 #define LPFC_HST_ISR0 0x0C18
750 #define LPFC_HST_ISR1 0x0C1C
751 #define LPFC_HST_ISR2 0x0C20
752 #define LPFC_HST_ISR3 0x0C24
753 #define LPFC_HST_ISR4 0x0C28
755 #define LPFC_HST_IMR0 0x0C48
756 #define LPFC_HST_IMR1 0x0C4C
757 #define LPFC_HST_IMR2 0x0C50
758 #define LPFC_HST_IMR3 0x0C54
759 #define LPFC_HST_IMR4 0x0C58
761 #define LPFC_HST_ISCR0 0x0C78
762 #define LPFC_HST_ISCR1 0x0C7C
763 #define LPFC_HST_ISCR2 0x0C80
764 #define LPFC_HST_ISCR3 0x0C84
765 #define LPFC_HST_ISCR4 0x0C88
803 * value. For UCNA ports running SLI4 and if_type 0, they reside in
809 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
810 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
811 #define LPFC_IF6_RQ_DOORBELL 0x0080
813 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
816 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
818 #define lpfc_rq_db_list_fm_id_SHIFT 0
819 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
822 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
824 #define lpfc_rq_db_ring_fm_id_SHIFT 0
825 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
828 #define LPFC_ULP0_WQ_DOORBELL 0x0040
829 #define LPFC_ULP1_WQ_DOORBELL 0x0060
831 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
834 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
836 #define lpfc_wq_db_list_fm_id_SHIFT 0
837 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
840 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
842 #define lpfc_wq_db_ring_fm_id_SHIFT 0
843 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
846 #define LPFC_IF6_WQ_DOORBELL 0x0040
848 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
851 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
854 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
856 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
857 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
860 #define LPFC_EQCQ_DOORBELL 0x0120
862 #define lpfc_eqcq_doorbell_se_MASK 0x0001
864 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
867 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
870 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
873 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
875 #define LPFC_QUEUE_TYPE_COMPLETION 0
878 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
880 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
881 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
884 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
886 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
887 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
890 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
895 #define LPFC_IF6_CQ_DOORBELL 0x00C0
897 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
899 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
902 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
905 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
907 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
908 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
911 #define LPFC_IF6_EQ_DOORBELL 0x0120
913 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
915 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
918 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
921 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
923 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
924 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
927 #define LPFC_BMBX 0x0160
929 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
932 #define lpfc_bmbx_hi_MASK 0x0001
934 #define lpfc_bmbx_rdy_SHIFT 0
935 #define lpfc_bmbx_rdy_MASK 0x0001
938 #define LPFC_MQ_DOORBELL 0x0140
939 #define LPFC_IF6_MQ_DOORBELL 0x0160
941 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
943 #define lpfc_mq_doorbell_id_SHIFT 0
944 #define lpfc_mq_doorbell_id_MASK 0xFFFF
949 #define lpfc_mbox_hdr_emb_SHIFT 0
950 #define lpfc_mbox_hdr_emb_MASK 0x00000001
953 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
964 #define lpfc_mbox_hdr_opcode_SHIFT 0
965 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
968 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
971 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
974 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
979 #define lpfc_mbox_hdr_version_SHIFT 0
980 #define lpfc_mbox_hdr_version_MASK 0x000000FF
983 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
986 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
990 #define LPFC_Q_CREATE_VERSION_0 0
991 #define LPFC_OPCODE_VERSION_0 0
996 #define lpfc_mbox_hdr_opcode_SHIFT 0
997 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
1000 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
1003 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
1006 #define lpfc_mbox_hdr_status_SHIFT 0
1007 #define lpfc_mbox_hdr_status_MASK 0x000000FF
1010 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
1012 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2
1014 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF
1016 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01
1017 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02
1035 #define LPFC_EXTENT_LOCAL 0
1036 #define LPFC_TIMEOUT_DEFAULT 0
1037 #define LPFC_EXTENT_VERSION_DEFAULT 0
1040 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
1041 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
1042 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
1043 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
1048 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
1049 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
1052 #define LPFC_MBOX_OPCODE_NA 0x00
1053 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
1054 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
1055 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
1056 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
1057 #define LPFC_MBOX_OPCODE_NOP 0x21
1058 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
1059 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1060 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1061 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1062 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1063 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1064 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1065 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1066 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1067 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1068 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1069 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1070 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1071 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1072 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1073 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1074 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E
1075 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1076 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1077 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1078 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1079 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1080 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1081 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1082 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1083 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1084 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1085 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1086 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1087 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1088 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1089 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1090 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1091 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1094 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1095 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1096 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1097 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1098 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1099 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1100 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1101 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1102 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1103 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1104 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1105 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1106 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1107 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1108 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1109 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1112 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1118 #define lpfc_eq_context_size_MASK 0x00000001
1120 #define LPFC_EQE_SIZE_4 0x0
1121 #define LPFC_EQE_SIZE_16 0x1
1123 #define lpfc_eq_context_valid_MASK 0x00000001
1126 #define lpfc_eq_context_autovalid_MASK 0x00000001
1130 #define lpfc_eq_context_count_MASK 0x00000003
1132 #define LPFC_EQ_CNT_256 0x0
1133 #define LPFC_EQ_CNT_512 0x1
1134 #define LPFC_EQ_CNT_1024 0x2
1135 #define LPFC_EQ_CNT_2048 0x3
1136 #define LPFC_EQ_CNT_4096 0x4
1139 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1161 #define lpfc_post_sgl_pages_xri_SHIFT 0
1162 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1165 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1200 struct lpfc_mbx_read_object { /* Version 0 */
1205 #define lpfc_mbx_rd_object_rlen_SHIFT 0
1206 #define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF
1218 #define lpfc_mbx_rd_object_eof_MASK 0x1
1229 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1230 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1237 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1238 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1262 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1263 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1284 #define lpfc_fwlog_enable_SHIFT 0
1285 #define lpfc_fwlog_enable_MASK 0x00000001
1288 #define lpfc_fwlog_loglvl_MASK 0x0000000F
1291 #define lpfc_fwlog_ra_WORD 0x00000008
1293 #define lpfc_fwlog_buffcnt_MASK 0x000000FF
1296 #define lpfc_fwlog_buffsz_MASK 0x000000FF
1299 #define lpfc_fwlog_acqe_SHIFT 0
1300 #define lpfc_fwlog_acqe_MASK 0x0000FFFF
1303 #define lpfc_fwlog_cqid_MASK 0x0000FFFF
1319 #define lpfc_cq_context_event_MASK 0x00000001
1322 #define lpfc_cq_context_valid_MASK 0x00000001
1325 #define lpfc_cq_context_count_MASK 0x00000003
1327 #define LPFC_CQ_CNT_256 0x0
1328 #define LPFC_CQ_CNT_512 0x1
1329 #define LPFC_CQ_CNT_1024 0x2
1330 #define LPFC_CQ_CNT_WORD7 0x3
1332 #define lpfc_cq_context_autovalid_MASK 0x00000001
1335 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1336 #define lpfc_cq_eq_id_MASK 0x000000FF
1338 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1339 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1351 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1353 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1354 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1361 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1362 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1374 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1376 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1377 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1381 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1384 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1387 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1390 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1393 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1396 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1399 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1403 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1406 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1408 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1409 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1413 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1415 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1416 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1420 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1422 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1423 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1427 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1429 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1430 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1434 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1436 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1437 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1441 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1443 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1444 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1448 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1450 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1451 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1455 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1457 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1458 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1462 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1464 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1465 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1472 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1474 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1475 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1486 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1487 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1506 struct { /* Version 0 Request */
1508 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1509 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1512 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1515 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1519 #define lpfc_mbx_wq_create_bua_SHIFT 0
1520 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1523 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1527 uint32_t word0; /* Word 0 is the same as in v0 */
1529 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1530 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1532 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1534 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1537 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1540 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1543 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1545 #define LPFC_WQ_WQE_SIZE_64 0x5
1546 #define LPFC_WQ_WQE_SIZE_128 0x6
1548 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1555 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1556 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1560 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1561 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1563 #define WQ_PCI_BAR_0_AND_1 0x00
1564 #define WQ_PCI_BAR_2_AND_3 0x01
1565 #define WQ_PCI_BAR_4_AND_5 0x02
1567 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1573 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1575 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1576 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1579 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1580 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1585 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1587 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1588 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1600 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1601 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1615 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1616 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1623 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1626 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1633 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1634 #define lpfc_rq_context_page_size_MASK 0x000000FF
1636 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1639 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1641 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1642 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1646 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF
1648 #define lpfc_rq_context_buf_size_SHIFT 0
1649 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1651 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1652 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1662 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1663 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1666 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1669 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1672 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1680 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1682 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1683 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1687 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1688 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1691 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1702 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1703 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1706 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1709 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1712 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1715 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1718 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1721 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1724 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1732 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1734 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1735 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1739 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1740 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1743 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1754 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1755 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1766 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1767 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1770 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1772 #define LPFC_MQ_RING_SIZE_16 0x5
1773 #define LPFC_MQ_RING_SIZE_32 0x6
1774 #define LPFC_MQ_RING_SIZE_64 0x7
1775 #define LPFC_MQ_RING_SIZE_128 0x8
1778 #define lpfc_mq_context_valid_MASK 0x00000001
1789 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1790 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1797 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1798 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1809 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1810 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1813 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1817 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1819 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1820 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1821 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1822 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1823 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1825 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1828 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1831 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1833 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1834 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1835 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1836 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1837 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1838 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1839 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1841 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1848 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1849 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1853 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1854 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1855 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1863 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1864 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1876 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1877 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1878 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1879 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1886 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1887 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1892 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1893 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1896 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1906 #define LPFC_FC_FCOE 0x00000007
1910 #define LPFC_FCOE_INI_MODE 0x00000040
1911 #define LPFC_FCOE_TGT_MODE 0x00000080
1912 #define LPFC_DUA_MODE 0x00000800
1914 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1915 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1932 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1933 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1936 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1939 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1942 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1947 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1954 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1955 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1958 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1967 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1968 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1971 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1973 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1976 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1979 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1993 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1994 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1996 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1997 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1998 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1999 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
2001 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
2004 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
2019 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
2022 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
2025 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
2026 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
2029 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
2032 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
2033 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
2036 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
2067 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
2068 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
2071 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
2076 #define lpfc_mbx_rsrc_cnt_SHIFT 0
2077 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
2101 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2102 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2113 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2114 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2117 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2128 #define lpfc_sli4_sge_offset_SHIFT 0
2129 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2132 #define lpfc_sli4_sge_type_MASK 0x0000000F
2134 #define LPFC_SGE_TYPE_DATA 0x0
2135 #define LPFC_SGE_TYPE_DIF 0x4
2136 #define LPFC_SGE_TYPE_LSP 0x5
2137 #define LPFC_SGE_TYPE_PEDIF 0x6
2138 #define LPFC_SGE_TYPE_PESEED 0x7
2139 #define LPFC_SGE_TYPE_DISEED 0x8
2140 #define LPFC_SGE_TYPE_ENC 0x9
2141 #define LPFC_SGE_TYPE_ATM 0xA
2142 #define LPFC_SGE_TYPE_SKIP 0xC
2144 #define lpfc_sli4_sge_last_MASK 0x00000001
2171 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2172 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2175 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2178 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2181 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2184 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2187 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2190 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2191 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2194 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2197 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2200 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2203 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2206 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2209 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2212 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2215 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2225 #define lpfc_fcf_record_mac_0_SHIFT 0
2226 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2229 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2232 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2235 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2238 #define lpfc_fcf_record_mac_4_SHIFT 0
2239 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2242 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2245 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2248 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2253 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2254 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2257 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2260 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2263 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2266 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2267 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2270 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2273 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2276 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2279 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2280 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2283 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2286 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2289 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2292 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2295 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2298 #define lpfc_fcf_record_fcf_index_SHIFT 0
2299 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2302 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2306 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2307 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2310 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2313 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2316 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2319 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2320 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2323 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2326 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2329 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2338 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2339 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2347 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2348 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2355 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2356 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2364 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2365 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2368 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2375 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2376 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2380 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2381 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2386 #define STATUS_SUCCESS 0x0
2387 #define STATUS_FAILED 0x1
2388 #define STATUS_ILLEGAL_REQUEST 0x2
2389 #define STATUS_ILLEGAL_FIELD 0x3
2390 #define STATUS_INSUFFICIENT_BUFFER 0x4
2391 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2392 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2393 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2394 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2395 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2396 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2397 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2398 #define STATUS_ASSERT_FAILED 0x1e
2399 #define STATUS_INVALID_SESSION 0x1f
2400 #define STATUS_INVALID_CONNECTION 0x20
2401 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2402 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2403 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2404 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2405 #define STATUS_FLASHROM_READ_FAILED 0x27
2406 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2407 #define STATUS_ERROR_ACITMAIN 0x2a
2408 #define STATUS_REBOOT_REQUIRED 0x2c
2409 #define STATUS_FCF_IN_USE 0x3a
2410 #define STATUS_FCF_TABLE_EMPTY 0x43
2416 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2417 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2418 #define ADD_STATUS_INVALID_REQUEST 0x4B
2419 #define ADD_STATUS_INVALID_OBJECT_NAME 0xA0
2420 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2429 #define lpfc_init_vfi_vr_MASK 0x00000001
2432 #define lpfc_init_vfi_vt_MASK 0x00000001
2435 #define lpfc_init_vfi_vf_MASK 0x00000001
2438 #define lpfc_init_vfi_vp_MASK 0x00000001
2440 #define lpfc_init_vfi_vfi_SHIFT 0
2441 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2445 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2447 #define lpfc_init_vfi_fcfi_SHIFT 0
2448 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2452 #define lpfc_init_vfi_pri_MASK 0x00000007
2455 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2459 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2462 #define MBX_VFI_IN_USE 0x9F02
2468 #define lpfc_reg_vfi_upd_MASK 0x00000001
2471 #define lpfc_reg_vfi_vp_MASK 0x00000001
2473 #define lpfc_reg_vfi_vfi_SHIFT 0
2474 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2478 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2480 #define lpfc_reg_vfi_fcfi_SHIFT 0
2481 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2488 #define lpfc_reg_vfi_nport_id_SHIFT 0
2489 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2492 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2495 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2502 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2504 #define lpfc_init_vpi_vpi_SHIFT 0
2505 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2512 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2513 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2517 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2518 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2521 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2524 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2527 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2530 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2534 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2535 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2538 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2539 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2542 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2545 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2548 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2551 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2552 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2555 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2558 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2561 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2568 #define lpfc_unreg_vfi_vfi_SHIFT 0
2569 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2575 #define lpfc_resume_rpi_index_SHIFT 0
2576 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2579 #define lpfc_resume_rpi_ii_MASK 0x00000003
2581 #define RESUME_INDEX_RPI 0
2588 #define REG_FCF_INVALID_QID 0xFFFF
2591 #define lpfc_reg_fcfi_info_index_SHIFT 0
2592 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2595 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2598 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2599 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2602 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2605 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2606 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2609 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2613 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2616 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2619 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2621 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2622 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2626 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2629 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2632 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2634 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2635 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2639 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2642 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2645 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2647 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2648 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2652 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2655 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2658 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2660 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2661 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2665 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2667 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2671 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2673 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2674 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2680 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2681 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2684 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2687 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2688 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2691 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2694 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2695 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2698 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2702 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2705 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2708 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2710 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2711 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2715 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2718 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2721 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2723 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2724 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2728 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2731 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2734 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2736 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2737 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2741 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2744 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2747 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2749 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2750 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2754 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2757 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2760 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2763 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2766 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2769 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2772 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2775 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2778 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2781 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2784 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2787 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2790 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2793 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2796 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2799 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2802 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2805 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2808 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2810 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2811 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2815 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2818 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2820 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2821 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2835 #define lpfc_unreg_fcfi_SHIFT 0
2836 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2843 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2846 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2849 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2851 #define LPFC_PREDCBX_CEE_MODE 0
2854 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2857 #define LPFC_G7_ASIC_1 0xd
2862 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2863 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2866 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2869 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2872 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2881 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2882 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2893 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2896 #define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001
2899 #define lpfc_mbx_rd_conf_wcs_MASK 0x00000001
2902 #define lpfc_mbx_rd_conf_acs_MASK 0x00000001
2905 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2906 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2909 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2911 #define LPFC_LNK_TYPE_GE 0
2914 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2917 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2920 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2923 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2926 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2929 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2933 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2934 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2938 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2939 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2942 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2946 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2947 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2950 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2953 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2956 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2957 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2962 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2963 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2966 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2969 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2970 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2973 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2976 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2977 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2980 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2983 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2984 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2987 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2991 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2994 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2995 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2998 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
3001 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
3002 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
3005 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
3011 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
3012 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
3015 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
3016 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
3019 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
3022 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
3025 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
3028 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
3031 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
3034 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
3037 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
3040 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
3043 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
3046 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
3049 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001
3052 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
3053 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
3056 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
3059 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
3062 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
3065 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
3068 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
3071 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
3074 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
3077 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
3080 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
3083 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001
3089 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
3090 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
3093 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
3096 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
3097 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
3100 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
3103 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
3104 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
3111 #define DMP_PAGE_A0 0xa0
3112 #define DMP_PAGE_A2 0xa2
3123 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3124 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3125 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3126 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3127 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3128 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3129 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3130 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3131 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3132 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3133 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3134 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3135 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3136 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3137 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3138 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3142 #define SSF_IDENTIFIER 0
3184 #define SSF_TEMP_HIGH_ALARM 0
3309 #define cfg_prot_type_SHIFT 0
3310 #define cfg_prot_type_MASK 0x000000FF
3313 #define cfg_ft_SHIFT 0
3314 #define cfg_ft_MASK 0x00000001
3317 #define cfg_sli_rev_MASK 0x0000000f
3320 #define cfg_sli_family_MASK 0x0000000f
3323 #define cfg_if_type_MASK 0x0000000f
3326 #define cfg_sli_hint_1_MASK 0x000000ff
3329 #define cfg_sli_hint_2_MASK 0x0000001f
3333 #define cfg_eqav_MASK 0x00000001
3338 #define cfg_cqv_MASK 0x00000003
3341 #define cfg_cqpsize_MASK 0x000000ff
3344 #define cfg_cqav_MASK 0x00000001
3349 #define cfg_mqv_MASK 0x00000003
3353 #define cfg_wqpcnt_SHIFT 0
3354 #define cfg_wqpcnt_MASK 0x0000000f
3357 #define cfg_wqsize_MASK 0x0000000f
3360 #define cfg_wqv_MASK 0x00000003
3363 #define cfg_wqpsize_MASK 0x000000ff
3368 #define cfg_rqv_MASK 0x00000003
3372 #define cfg_rq_db_window_MASK 0x0000000f
3375 #define cfg_fcoe_SHIFT 0
3376 #define cfg_fcoe_MASK 0x00000001
3379 #define cfg_ext_MASK 0x00000001
3382 #define cfg_hdrr_MASK 0x00000001
3385 #define cfg_phwq_MASK 0x00000001
3388 #define cfg_oas_MASK 0x00000001
3391 #define cfg_loopbk_scope_MASK 0x0000000f
3395 #define cfg_sgl_page_cnt_SHIFT 0
3396 #define cfg_sgl_page_cnt_MASK 0x0000000f
3399 #define cfg_sgl_page_size_MASK 0x000000ff
3402 #define cfg_sgl_pp_align_MASK 0x000000ff
3409 #define cfg_ext_embed_cb_SHIFT 0
3410 #define cfg_ext_embed_cb_MASK 0x00000001
3413 #define cfg_mds_diags_MASK 0x00000001
3416 #define cfg_nvme_MASK 0x00000001
3419 #define cfg_xib_MASK 0x00000001
3422 #define cfg_xpsgl_MASK 0x00000001
3425 #define cfg_eqdr_MASK 0x00000001
3428 #define cfg_nosr_MASK 0x00000001
3431 #define cfg_bv1s_MASK 0x00000001
3435 #define cfg_nsler_MASK 0x00000001
3438 #define cfg_pvl_MASK 0x00000001
3442 #define cfg_pbde_MASK 0x00000001
3446 #define cfg_max_tow_xri_SHIFT 0
3447 #define cfg_max_tow_xri_MASK 0x0000ffff
3451 #define cfg_mi_ver_SHIFT 0
3452 #define cfg_mi_ver_MASK 0x0000ffff
3455 #define cfg_cmf_MASK 0x000000ff
3462 #define cfg_frag_field_offset_SHIFT 0
3463 #define cfg_frag_field_offset_MASK 0x0000ffff
3467 #define cfg_frag_field_size_MASK 0x0000ffff
3471 #define cfg_sgl_field_offset_SHIFT 0
3472 #define cfg_sgl_field_offset_MASK 0x0000ffff
3476 #define cfg_sgl_field_size_MASK 0x0000ffff
3484 #define LPFC_SET_UE_RECOVERY 0x10
3485 #define LPFC_SET_MDS_DIAGS 0x12
3486 #define LPFC_SET_DUAL_DUMP 0x1e
3487 #define LPFC_SET_CGN_SIGNAL 0x1f
3488 #define LPFC_SET_ENABLE_MI 0x21
3489 #define LPFC_SET_LD_SIGNAL 0x23
3490 #define LPFC_SET_ENABLE_CMF 0x24
3496 #define lpfc_mbx_set_feature_UER_SHIFT 0
3497 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3500 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3503 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3505 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0
3506 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff
3508 #define lpfc_mbx_set_feature_dd_SHIFT 0
3509 #define lpfc_mbx_set_feature_dd_MASK 0x00000001
3512 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3514 #define LPFC_DISABLE_DUAL_DUMP 0
3517 #define lpfc_mbx_set_feature_cmf_SHIFT 0
3518 #define lpfc_mbx_set_feature_cmf_MASK 0x00000001
3520 #define lpfc_mbx_set_feature_lds_qry_SHIFT 0
3521 #define lpfc_mbx_set_feature_lds_qry_MASK 0x00000001
3524 #define lpfc_mbx_set_feature_mi_SHIFT 0
3525 #define lpfc_mbx_set_feature_mi_MASK 0x0000ffff
3528 #define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff
3531 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3532 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3535 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3537 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0
3538 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff
3541 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0
3542 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff
3549 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3550 #define LPFC_SET_HOST_DATE_TIME 0x4
3556 #define lpfc_mbx_set_host_month_MASK 0xFF
3559 #define lpfc_mbx_set_host_day_MASK 0xFF
3561 #define lpfc_mbx_set_host_year_SHIFT 0
3562 #define lpfc_mbx_set_host_year_MASK 0xFF
3566 #define lpfc_mbx_set_host_hour_MASK 0xFF
3569 #define lpfc_mbx_set_host_min_MASK 0xFF
3571 #define lpfc_mbx_set_host_sec_SHIFT 0
3572 #define lpfc_mbx_set_host_sec_MASK 0xFF
3590 #define lpfc_mbx_set_trunk_mode_SHIFT 0
3591 #define lpfc_mbx_set_trunk_mode_MASK 0xFF
3605 #define lpfc_mbx_reg_cgn_buf_type_SHIFT 0
3606 #define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF
3609 #define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF
3623 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3624 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3626 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3628 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3631 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3632 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3636 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3637 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3640 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3643 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3646 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3647 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3653 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3654 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3656 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3658 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3660 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3664 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3665 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3668 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3671 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3672 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3675 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3678 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3679 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3682 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3685 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3686 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3689 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3692 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3693 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3696 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3706 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3707 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3710 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3713 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3716 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3719 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3737 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3738 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3739 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3751 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3752 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3753 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3757 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3758 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3761 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3775 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3776 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3779 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3782 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff
3799 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3800 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3803 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3806 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3810 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3811 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3814 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3817 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3820 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3821 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3824 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3827 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3828 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3831 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3834 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3837 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3840 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3847 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3848 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3851 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3854 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3855 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3858 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3861 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3862 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3865 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3868 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3871 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3875 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3876 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3891 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3892 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3897 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3898 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3901 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3904 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3907 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3909 #define LPFC_LINK_NUMBER_0 0
3918 #define MB_CQE_STATUS_SUCCESS 0x0
3919 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3920 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3921 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3922 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3923 #define MB_CQE_STATUS_DMA_FAILED 0x5
3933 #define lpfc_wr_object_eof_MASK 0x00000001
3936 #define lpfc_wr_object_eas_MASK 0x00000001
3938 #define lpfc_wr_object_write_length_SHIFT 0
3939 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3949 #define lpfc_wr_object_change_status_SHIFT 0
3950 #define lpfc_wr_object_change_status_MASK 0x000000FF
3952 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3953 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3954 #define LPFC_CHANGE_STATUS_FW_RESET 0x02
3955 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3956 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3958 #define lpfc_wr_object_csf_MASK 0x00000001
3968 #define lpfc_mqe_status_MASK 0x0000FFFF
3971 #define lpfc_mqe_command_MASK 0x000000FF
4036 #define lpfc_mcqe_status_SHIFT 0
4037 #define lpfc_mcqe_status_MASK 0x0000FFFF
4040 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
4046 #define lpfc_trailer_valid_MASK 0x00000001
4049 #define lpfc_trailer_async_MASK 0x00000001
4052 #define lpfc_trailer_hpi_MASK 0x00000001
4055 #define lpfc_trailer_completed_MASK 0x00000001
4058 #define lpfc_trailer_consumed_MASK 0x00000001
4061 #define lpfc_trailer_type_MASK 0x000000FF
4064 #define lpfc_trailer_code_MASK 0x000000FF
4066 #define LPFC_TRAILER_CODE_LINK 0x1
4067 #define LPFC_TRAILER_CODE_FCOE 0x2
4068 #define LPFC_TRAILER_CODE_DCBX 0x3
4069 #define LPFC_TRAILER_CODE_GRP5 0x5
4070 #define LPFC_TRAILER_CODE_FC 0x10
4071 #define LPFC_TRAILER_CODE_SLI 0x11
4072 #define LPFC_TRAILER_CODE_CMSTAT 0x13
4078 #define lpfc_acqe_link_speed_MASK 0x000000FF
4080 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
4081 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
4082 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
4083 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
4084 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
4085 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
4086 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
4087 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
4088 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
4090 #define lpfc_acqe_link_duplex_MASK 0x000000FF
4092 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
4093 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
4094 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
4096 #define lpfc_acqe_link_status_MASK 0x000000FF
4098 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
4099 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
4100 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
4101 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
4103 #define lpfc_acqe_link_type_MASK 0x00000003
4105 #define lpfc_acqe_link_number_SHIFT 0
4106 #define lpfc_acqe_link_number_MASK 0x0000003F
4109 #define lpfc_acqe_link_fault_SHIFT 0
4110 #define lpfc_acqe_link_fault_MASK 0x000000FF
4112 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
4113 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
4114 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
4115 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
4117 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
4121 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
4122 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
4128 #define lpfc_acqe_fip_fcf_count_SHIFT 0
4129 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
4132 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
4136 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
4137 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
4138 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
4139 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
4140 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
4153 #define lpfc_acqe_grp5_type_MASK 0x00000003
4155 #define lpfc_acqe_grp5_number_SHIFT 0
4156 #define lpfc_acqe_grp5_number_MASK 0x0000003F
4160 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
4171 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
4173 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
4174 #define LPFC_FC_LA_SPEED_1G 0x1
4175 #define LPFC_FC_LA_SPEED_2G 0x2
4176 #define LPFC_FC_LA_SPEED_4G 0x4
4177 #define LPFC_FC_LA_SPEED_8G 0x8
4178 #define LPFC_FC_LA_SPEED_10G 0xA
4179 #define LPFC_FC_LA_SPEED_16G 0x10
4180 #define LPFC_FC_LA_SPEED_32G 0x20
4181 #define LPFC_FC_LA_SPEED_64G 0x21
4182 #define LPFC_FC_LA_SPEED_128G 0x22
4183 #define LPFC_FC_LA_SPEED_256G 0x23
4185 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
4187 #define LPFC_FC_LA_TOP_UNKOWN 0x0
4188 #define LPFC_FC_LA_TOP_P2P 0x1
4189 #define LPFC_FC_LA_TOP_FCAL 0x2
4190 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
4191 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
4193 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
4195 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
4196 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4197 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4198 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4199 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4200 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4201 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4202 #define LPFC_FC_LA_TYPE_ACTIVATE_FAIL 0x8
4203 #define LPFC_FC_LA_TYPE_LINK_RESET_PRTCL_EVT 0x9
4205 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4207 #define LPFC_LINK_TYPE_ETHERNET 0x0
4208 #define LPFC_LINK_TYPE_FC 0x1
4209 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4210 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4213 /* Attention Type is 0x07 (Trunking Event) word0 */
4215 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4218 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4221 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4224 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4227 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4230 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4233 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4236 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4240 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4242 #define lpfc_acqe_fc_la_fault_SHIFT 0
4243 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4246 #define lpfc_acqe_fc_la_link_status_MASK 0x0000007F
4248 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4249 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4252 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4254 #define LPFC_FC_LA_FAULT_NONE 0x0
4255 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4256 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4259 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4260 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4266 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4267 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4270 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4273 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4276 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4279 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4280 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4283 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4286 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4289 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4292 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4295 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4298 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4301 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4304 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4305 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4306 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4307 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4308 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4309 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4314 #define lpfc_warn_acqe_SHIFT 0
4315 #define lpfc_warn_acqe_MASK 0x7FFFFFFF
4318 #define lpfc_imm_acqe_MASK 0x1
4330 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4331 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4332 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4333 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4334 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4335 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4336 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4337 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE
4338 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4339 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4340 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11
4341 #define LPFC_SLI_EVENT_TYPE_RD_SIGNAL 0x12
4358 #define NO_XRI 0xffff
4362 #define wqe_xri_tag_SHIFT 0
4363 #define wqe_xri_tag_MASK 0x0000FFFF
4366 #define wqe_ctxt_tag_MASK 0x0000FFFF
4369 #define wqe_dif_SHIFT 0
4370 #define wqe_dif_MASK 0x00000003
4376 #define wqe_ct_MASK 0x00000003
4379 #define wqe_status_MASK 0x0000000f
4382 #define wqe_cmnd_MASK 0x000000ff
4385 #define wqe_class_MASK 0x00000007
4388 #define wqe_ar_MASK 0x00000001
4394 #define wqe_pu_MASK 0x00000003
4397 #define wqe_erp_MASK 0x00000001
4403 #define wqe_lnk_MASK 0x00000001
4406 #define wqe_tmo_MASK 0x000000ff
4410 #define wqe_reqtag_SHIFT 0
4411 #define wqe_reqtag_MASK 0x0000FFFF
4414 #define wqe_temp_rpi_MASK 0x0000FFFF
4417 #define wqe_rcvoxid_MASK 0x0000FFFF
4420 #define wqe_sof_MASK 0x000000FF
4423 #define wqe_eof_MASK 0x000000FF
4426 #define wqe_ebde_cnt_SHIFT 0
4427 #define wqe_ebde_cnt_MASK 0x0000000f
4430 #define wqe_xchg_MASK 0x00000001
4432 #define LPFC_SCSI_XCHG 0x0
4433 #define LPFC_NVME_XCHG 0x1
4435 #define wqe_appid_MASK 0x00000001
4438 #define wqe_oas_MASK 0x00000001
4441 #define wqe_lenloc_MASK 0x00000003
4443 #define LPFC_WQE_LENLOC_NONE 0
4448 #define wqe_qosd_MASK 0x00000001
4451 #define wqe_xbl_MASK 0x00000001
4454 #define wqe_iod_MASK 0x00000001
4456 #define LPFC_WQE_IOD_NONE 0
4457 #define LPFC_WQE_IOD_WRITE 0
4460 #define wqe_dbde_MASK 0x00000001
4463 #define wqe_wqes_MASK 0x00000001
4467 #define wqe_wqid_MASK 0x00007fff
4470 #define wqe_pri_MASK 0x00000007
4473 #define wqe_pv_MASK 0x00000001
4476 #define wqe_xc_MASK 0x00000001
4479 #define wqe_sr_MASK 0x00000001
4482 #define wqe_ccpe_MASK 0x00000001
4485 #define wqe_ccp_MASK 0x000000ff
4488 #define wqe_cmd_type_SHIFT 0
4489 #define wqe_cmd_type_MASK 0x0000000f
4492 #define wqe_els_id_MASK 0x00000007
4495 #define wqe_irsp_MASK 0x00000001
4498 #define wqe_pbde_MASK 0x00000001
4501 #define wqe_sup_MASK 0x00000001
4504 #define wqe_ffrq_MASK 0x00000001
4507 #define wqe_wqec_MASK 0x00000001
4510 #define wqe_irsplen_MASK 0x0000000f
4513 #define wqe_cqid_MASK 0x0000ffff
4515 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4520 #define wqe_els_did_SHIFT 0
4521 #define wqe_els_did_MASK 0x00FFFFFF
4524 #define wqe_xmit_bls_pt_MASK 0x00000003
4527 #define wqe_xmit_bls_ar_MASK 0x00000001
4530 #define wqe_xmit_bls_xo_MASK 0x00000001
4555 #define els_req64_sid_SHIFT 0
4556 #define els_req64_sid_MASK 0x00FFFFFF
4559 #define els_req64_sp_MASK 0x00000001
4562 #define els_req64_vf_MASK 0x00000001
4568 #define els_req64_vfid_MASK 0x00000FFF
4571 #define els_req64_pri_MASK 0x00000007
4575 #define els_req64_hopcnt_MASK 0x000000ff
4585 #define els_rsp64_sid_SHIFT 0
4586 #define els_rsp64_sid_MASK 0x00FFFFFF
4589 #define els_rsp64_sp_MASK 0x00000001
4594 #define wqe_rsp_temp_rpi_SHIFT 0
4595 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4604 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4607 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4610 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4611 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4614 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4617 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4620 #define xmit_bls_rsp64_rxid_SHIFT 0
4621 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4624 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4627 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4628 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4631 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4638 #define xmit_bls_rsp64_temprpi_SHIFT 0
4639 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4647 #define wqe_si_MASK 0x000000001
4650 #define wqe_la_MASK 0x000000001
4653 #define wqe_xo_MASK 0x000000001
4656 #define wqe_ls_MASK 0x000000001
4659 #define wqe_dfctl_MASK 0x0000000ff
4662 #define wqe_type_MASK 0x0000000ff
4665 #define wqe_rctl_MASK 0x0000000ff
4705 #define prli_acc_rsp_code_MASK 0x0000000f
4708 #define prli_estabImagePair_MASK 0x00000001
4711 #define prli_type_code_ext_MASK 0x000000ff
4714 #define prli_type_code_MASK 0x000000ff
4720 #define prli_fba_SHIFT 0
4721 #define prli_fba_MASK 0x00000001
4724 #define prli_disc_MASK 0x00000001
4727 #define prli_tgt_MASK 0x00000001
4730 #define prli_init_MASK 0x00000001
4733 #define prli_conf_MASK 0x00000001
4736 #define prli_nsler_MASK 0x00000001
4739 #define prli_fb_sz_SHIFT 0
4740 #define prli_fb_sz_MASK 0x0000ffff
4746 uint32_t rsrvd[5]; /* words 0-4 */
4758 #define cmf_sync_interval_SHIFT 0
4759 #define cmf_sync_interval_MASK 0x00000ffff
4762 #define cmf_sync_afpin_MASK 0x000000001
4765 #define cmf_sync_asig_MASK 0x000000001
4768 #define cmf_sync_op_MASK 0x00000000f
4771 #define cmf_sync_ver_MASK 0x0000000ff
4776 #define cmf_sync_wsigmax_SHIFT 0
4777 #define cmf_sync_wsigmax_MASK 0x00000ffff
4780 #define cmf_sync_wsigcnt_MASK 0x00000ffff
4785 #define cmf_sync_cmnd_MASK 0x0000000ff
4789 #define cmf_sync_reqtag_SHIFT 0
4790 #define cmf_sync_reqtag_MASK 0x00000ffff
4793 #define cmf_sync_wfpinmax_MASK 0x0000000ff
4796 #define cmf_sync_wfpincnt_MASK 0x0000000ff
4800 #define cmf_sync_qosd_MASK 0x00000001
4803 #define cmf_sync_cmd_type_SHIFT 0
4804 #define cmf_sync_cmd_type_MASK 0x0000000f
4807 #define cmf_sync_wqec_MASK 0x00000001
4810 #define cmf_sync_cqid_MASK 0x0000ffff
4815 #define cmf_sync_period_MASK 0x000000ff
4824 #define abort_cmd_ia_SHIFT 0
4825 #define abort_cmd_ia_MASK 0x000000001
4828 #define abort_cmd_criteria_MASK 0x0000000ff
4840 #define cmd_buff_len_MASK 0x00000ffff
4842 #define payload_offset_len_SHIFT 0
4843 #define payload_offset_len_MASK 0x0000ffff
4856 #define cmd_buff_len_MASK 0x00000ffff
4858 #define payload_offset_len_SHIFT 0
4859 #define payload_offset_len_MASK 0x0000ffff
4869 struct ulp_bde64 bde; /* words 0-2 */
4872 #define cmd_buff_len_MASK 0x00000ffff
4874 #define payload_offset_len_SHIFT 0
4875 #define payload_offset_len_MASK 0x0000ffff
4912 #define CMD_SEND_FRAME 0xE1
4915 struct ulp_bde64 bde; /* words 0-2 */
4985 #define MAGIC_NUMBER_G6 0xFEAA0003
4986 #define MAGIC_NUMBER_G7 0xFEAA0005
4987 #define MAGIC_NUMBER_G7P 0xFEAA0020
4994 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4997 #define lpfc_grp_hdr_id_MASK 0x000000FF
5005 #define FCP_COMMAND 0x0
5006 #define NVME_READ_CMD 0x0
5007 #define FCP_COMMAND_DATA_OUT 0x1
5008 #define NVME_WRITE_CMD 0x1
5009 #define COMMAND_DATA_IN 0x0
5010 #define COMMAND_DATA_OUT 0x1
5011 #define FCP_COMMAND_TRECEIVE 0x2
5012 #define FCP_COMMAND_TRSP 0x3
5013 #define FCP_COMMAND_TSEND 0x7
5014 #define OTHER_COMMAND 0x8
5015 #define CMF_SYNC_COMMAND 0xA
5016 #define ELS_COMMAND_NON_FIP 0xC
5017 #define ELS_COMMAND_FIP 0xD
5019 #define LPFC_NVME_EMBED_CMD 0x0
5020 #define LPFC_NVME_EMBED_WRITE 0x1
5021 #define LPFC_NVME_EMBED_READ 0x2
5024 #define CMD_ABORT_XRI_WQE 0x0F
5025 #define CMD_XMIT_SEQUENCE64_WQE 0x82
5026 #define CMD_XMIT_BCAST64_WQE 0x84
5027 #define CMD_ELS_REQUEST64_WQE 0x8A
5028 #define CMD_XMIT_ELS_RSP64_WQE 0x95
5029 #define CMD_XMIT_BLS_RSP64_WQE 0x97
5030 #define CMD_FCP_IWRITE64_WQE 0x98
5031 #define CMD_FCP_IREAD64_WQE 0x9A
5032 #define CMD_FCP_ICMND64_WQE 0x9C
5033 #define CMD_FCP_TSEND64_WQE 0x9F
5034 #define CMD_FCP_TRECEIVE64_WQE 0xA1
5035 #define CMD_FCP_TRSP64_WQE 0xA3
5036 #define CMD_GEN_REQUEST64_WQE 0xC2
5037 #define CMD_CMF_SYNC_WQE 0xE8
5039 #define CMD_WQE_MASK 0xff
5051 #define ELS_DTAG_LNK_FAULT_CAP 0x0001000D
5054 #define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F