1 // SPDX-License-Identifier: GPL-2.0+
3  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
45 /* Magic value to enable writes on jz4780 */
75 	return readl(rtc->base + reg);  in jz4740_rtc_reg_read()
80 	uint32_t ctrl;  in jz4740_rtc_wait_write_ready()  local
82 	return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl,  in jz4740_rtc_wait_write_ready()
83 				  ctrl & JZ_RTC_CTRL_WRDY, 0, 1000);  in jz4740_rtc_wait_write_ready()
88 	uint32_t ctrl;  in jz4780_rtc_enable_write()  local
95 	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);  in jz4780_rtc_enable_write()
97 	return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl,  in jz4780_rtc_enable_write()
98 				  ctrl & JZ_RTC_WENR_WEN, 0, 1000);  in jz4780_rtc_enable_write()
106 	if (rtc->type >= ID_JZ4760)  in jz4740_rtc_reg_write()
111 		writel(val, rtc->base + reg);  in jz4740_rtc_reg_write()
121 	uint32_t ctrl;  in jz4740_rtc_ctrl_set_bits()  local
123 	spin_lock_irqsave(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
125 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_ctrl_set_bits()
128 	ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;  in jz4740_rtc_ctrl_set_bits()
131 		ctrl |= mask;  in jz4740_rtc_ctrl_set_bits()
133 		ctrl &= ~mask;  in jz4740_rtc_ctrl_set_bits()
135 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);  in jz4740_rtc_ctrl_set_bits()
137 	spin_unlock_irqrestore(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
149 		return -EINVAL;  in jz4740_rtc_read_time()
158 	while (secs != secs2 && --timeout) {  in jz4740_rtc_read_time()
164 		return -EIO;  in jz4740_rtc_read_time()
187 	uint32_t ctrl;  in jz4740_rtc_read_alarm()  local
191 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_read_alarm()
193 	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);  in jz4740_rtc_read_alarm()
194 	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);  in jz4740_rtc_read_alarm()
196 	rtc_time64_to_tm(secs, &alrm->time);  in jz4740_rtc_read_alarm()
205 	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));  in jz4740_rtc_set_alarm()
210 			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);  in jz4740_rtc_set_alarm()
215 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)  in jz4740_rtc_alarm_irq_enable()  argument
218 	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);  in jz4740_rtc_alarm_irq_enable()
232 	uint32_t ctrl;  in jz4740_rtc_irq()  local
235 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);  in jz4740_rtc_irq()
237 	if (ctrl & JZ_RTC_CTRL_1HZ)  in jz4740_rtc_irq()
240 	if (ctrl & JZ_RTC_CTRL_AF)  in jz4740_rtc_irq()
243 	rtc_update_irq(rtc->rtc, 1, events);  in jz4740_rtc_irq()
263 	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
264 	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
265 	{ .compatible = "ingenic,jz4770-rtc", .data = (void *)ID_JZ4780 },
266 	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
279 	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",  in jz4740_rtc_set_wakeup_params()
281 	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",  in jz4740_rtc_set_wakeup_params()
285 	 * Set minimum wakeup pin assertion time: 100 ms.  in jz4740_rtc_set_wakeup_params()
296 	 * Set reset pin low-level assertion time after wakeup: 60 ms.  in jz4740_rtc_set_wakeup_params()
334 	.enable = jz4740_rtc_clk32k_enable,
341 	struct device *dev = &pdev->dev;  in jz4740_rtc_probe()
342 	struct device_node *np = dev->of_node;  in jz4740_rtc_probe()
350 		return -ENOMEM;  in jz4740_rtc_probe()
352 	rtc->type = (uintptr_t)device_get_match_data(dev);  in jz4740_rtc_probe()
358 	rtc->base = devm_platform_ioremap_resource(pdev, 0);  in jz4740_rtc_probe()
359 	if (IS_ERR(rtc->base))  in jz4740_rtc_probe()
360 		return PTR_ERR(rtc->base);  in jz4740_rtc_probe()
366 	spin_lock_init(&rtc->lock);  in jz4740_rtc_probe()
376 	rtc->rtc = devm_rtc_allocate_device(dev);  in jz4740_rtc_probe()
377 	if (IS_ERR(rtc->rtc))  in jz4740_rtc_probe()
378 		return dev_err_probe(dev, PTR_ERR(rtc->rtc),  in jz4740_rtc_probe()
381 	rtc->rtc->ops = &jz4740_rtc_ops;  in jz4740_rtc_probe()
382 	rtc->rtc->range_max = U32_MAX;  in jz4740_rtc_probe()
388 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);  in jz4740_rtc_probe()
390 	ret = devm_rtc_register_device(rtc->rtc);  in jz4740_rtc_probe()
395 			       pdev->name, rtc);  in jz4740_rtc_probe()
408 	if (device_property_present(dev, "#clock-cells")) {  in jz4740_rtc_probe()
409 		rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk),  in jz4740_rtc_probe()
412 		ret = devm_clk_hw_register(dev, &rtc->clk32k);  in jz4740_rtc_probe()
418 						  &rtc->clk32k);  in jz4740_rtc_probe()
430 		.name  = "jz4740-rtc",
437 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
440 MODULE_ALIAS("platform:jz4740-rtc");