Lines Matching +full:pwm +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * EHRPWM PWM driver
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
10 #include <linux/pwm.h>
122 static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) in ehrpwm_read() argument
124 return readw(base + offset); in ehrpwm_read()
127 static inline void ehrpwm_write(void __iomem *base, unsigned int offset, in ehrpwm_write() argument
130 writew(value, base + offset); in ehrpwm_write()
133 static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, in ehrpwm_modify() argument
138 val = readw(base + offset); in ehrpwm_modify()
141 writew(val, base + offset); in ehrpwm_modify()
145 * set_prescale_div - Set up the prescaler divider function
187 * Configure PWM output to HIGH/LOW level on counter in configure_polarity()
196 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
204 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
211 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); in configure_polarity()
218 static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in ehrpwm_pwm_config() argument
228 return -ERANGE; in ehrpwm_pwm_config()
230 c = pc->clk_rate; in ehrpwm_pwm_config()
239 c = pc->clk_rate; in ehrpwm_pwm_config()
246 * Period values should be same for multiple PWM channels as IP uses in ehrpwm_pwm_config()
250 if (pc->period_cycles[i] && in ehrpwm_pwm_config()
251 (pc->period_cycles[i] != period_cycles)) { in ehrpwm_pwm_config()
256 if (i == pwm->hwpwm) in ehrpwm_pwm_config()
259 dev_err(chip->dev, in ehrpwm_pwm_config()
262 return -EINVAL; in ehrpwm_pwm_config()
266 pc->period_cycles[pwm->hwpwm] = period_cycles; in ehrpwm_pwm_config()
268 /* Configure clock prescaler to support Low frequency PWM wave */ in ehrpwm_pwm_config()
271 dev_err(chip->dev, "Unsupported values\n"); in ehrpwm_pwm_config()
272 return -EINVAL; in ehrpwm_pwm_config()
275 pm_runtime_get_sync(chip->dev); in ehrpwm_pwm_config()
278 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); in ehrpwm_pwm_config()
285 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); in ehrpwm_pwm_config()
287 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); in ehrpwm_pwm_config()
289 /* Configure ehrpwm counter for up-count mode */ in ehrpwm_pwm_config()
290 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, in ehrpwm_pwm_config()
293 if (pwm->hwpwm == 1) in ehrpwm_pwm_config()
300 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); in ehrpwm_pwm_config()
302 pm_runtime_put_sync(chip->dev); in ehrpwm_pwm_config()
308 struct pwm_device *pwm, in ehrpwm_pwm_set_polarity() argument
314 pc->polarity[pwm->hwpwm] = polarity; in ehrpwm_pwm_set_polarity()
319 static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in ehrpwm_pwm_enable() argument
325 /* Leave clock enabled on enabling PWM */ in ehrpwm_pwm_enable()
326 pm_runtime_get_sync(chip->dev); in ehrpwm_pwm_enable()
328 /* Disabling Action Qualifier on PWM output */ in ehrpwm_pwm_enable()
329 if (pwm->hwpwm) { in ehrpwm_pwm_enable()
338 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_enable()
341 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); in ehrpwm_pwm_enable()
344 configure_polarity(pc, pwm->hwpwm); in ehrpwm_pwm_enable()
347 ret = clk_enable(pc->tbclk); in ehrpwm_pwm_enable()
349 dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n", in ehrpwm_pwm_enable()
350 dev_name(pc->chip.dev), ret); in ehrpwm_pwm_enable()
357 static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in ehrpwm_pwm_disable() argument
362 /* Action Qualifier puts PWM output low forcefully */ in ehrpwm_pwm_disable()
363 if (pwm->hwpwm) { in ehrpwm_pwm_disable()
372 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_disable()
374 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); in ehrpwm_pwm_disable()
377 * Action Qualifier control on PWM output from next TBCLK in ehrpwm_pwm_disable()
379 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_disable()
382 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); in ehrpwm_pwm_disable()
384 /* Disabling TBCLK on PWM disable */ in ehrpwm_pwm_disable()
385 clk_disable(pc->tbclk); in ehrpwm_pwm_disable()
387 /* Disable clock on PWM disable */ in ehrpwm_pwm_disable()
388 pm_runtime_put_sync(chip->dev); in ehrpwm_pwm_disable()
391 static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in ehrpwm_pwm_free() argument
395 if (pwm_is_enabled(pwm)) { in ehrpwm_pwm_free()
396 dev_warn(chip->dev, "Removing PWM device without disabling\n"); in ehrpwm_pwm_free()
397 pm_runtime_put_sync(chip->dev); in ehrpwm_pwm_free()
401 pc->period_cycles[pwm->hwpwm] = 0; in ehrpwm_pwm_free()
404 static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in ehrpwm_pwm_apply() argument
408 bool enabled = pwm->state.enabled; in ehrpwm_pwm_apply()
410 if (state->polarity != pwm->state.polarity) { in ehrpwm_pwm_apply()
412 ehrpwm_pwm_disable(chip, pwm); in ehrpwm_pwm_apply()
416 err = ehrpwm_pwm_set_polarity(chip, pwm, state->polarity); in ehrpwm_pwm_apply()
421 if (!state->enabled) { in ehrpwm_pwm_apply()
423 ehrpwm_pwm_disable(chip, pwm); in ehrpwm_pwm_apply()
427 err = ehrpwm_pwm_config(chip, pwm, state->duty_cycle, state->period); in ehrpwm_pwm_apply()
432 err = ehrpwm_pwm_enable(chip, pwm); in ehrpwm_pwm_apply()
443 { .compatible = "ti,am3352-ehrpwm" },
444 { .compatible = "ti,am33xx-ehrpwm" },
451 struct device_node *np = pdev->dev.of_node; in ehrpwm_pwm_probe()
456 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); in ehrpwm_pwm_probe()
458 return -ENOMEM; in ehrpwm_pwm_probe()
460 clk = devm_clk_get(&pdev->dev, "fck"); in ehrpwm_pwm_probe()
462 if (of_device_is_compatible(np, "ti,am33xx-ecap")) { in ehrpwm_pwm_probe()
463 dev_warn(&pdev->dev, "Binding is obsolete.\n"); in ehrpwm_pwm_probe()
464 clk = devm_clk_get(pdev->dev.parent, "fck"); in ehrpwm_pwm_probe()
469 return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Failed to get fck\n"); in ehrpwm_pwm_probe()
471 pc->clk_rate = clk_get_rate(clk); in ehrpwm_pwm_probe()
472 if (!pc->clk_rate) { in ehrpwm_pwm_probe()
473 dev_err(&pdev->dev, "failed to get clock rate\n"); in ehrpwm_pwm_probe()
474 return -EINVAL; in ehrpwm_pwm_probe()
477 pc->chip.dev = &pdev->dev; in ehrpwm_pwm_probe()
478 pc->chip.ops = &ehrpwm_pwm_ops; in ehrpwm_pwm_probe()
479 pc->chip.npwm = NUM_PWM_CHANNEL; in ehrpwm_pwm_probe()
481 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ehrpwm_pwm_probe()
482 if (IS_ERR(pc->mmio_base)) in ehrpwm_pwm_probe()
483 return PTR_ERR(pc->mmio_base); in ehrpwm_pwm_probe()
486 pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); in ehrpwm_pwm_probe()
487 if (IS_ERR(pc->tbclk)) in ehrpwm_pwm_probe()
488 return dev_err_probe(&pdev->dev, PTR_ERR(pc->tbclk), "Failed to get tbclk\n"); in ehrpwm_pwm_probe()
490 ret = clk_prepare(pc->tbclk); in ehrpwm_pwm_probe()
492 dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret); in ehrpwm_pwm_probe()
496 ret = pwmchip_add(&pc->chip); in ehrpwm_pwm_probe()
498 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); in ehrpwm_pwm_probe()
503 pm_runtime_enable(&pdev->dev); in ehrpwm_pwm_probe()
508 clk_unprepare(pc->tbclk); in ehrpwm_pwm_probe()
517 pwmchip_remove(&pc->chip); in ehrpwm_pwm_remove()
519 clk_unprepare(pc->tbclk); in ehrpwm_pwm_remove()
521 pm_runtime_disable(&pdev->dev); in ehrpwm_pwm_remove()
526 pm_runtime_get_sync(pc->chip.dev); in ehrpwm_pwm_save_context()
528 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); in ehrpwm_pwm_save_context()
529 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); in ehrpwm_pwm_save_context()
530 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); in ehrpwm_pwm_save_context()
531 pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); in ehrpwm_pwm_save_context()
532 pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); in ehrpwm_pwm_save_context()
533 pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); in ehrpwm_pwm_save_context()
534 pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); in ehrpwm_pwm_save_context()
535 pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); in ehrpwm_pwm_save_context()
537 pm_runtime_put_sync(pc->chip.dev); in ehrpwm_pwm_save_context()
542 ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); in ehrpwm_pwm_restore_context()
543 ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); in ehrpwm_pwm_restore_context()
544 ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); in ehrpwm_pwm_restore_context()
545 ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); in ehrpwm_pwm_restore_context()
546 ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); in ehrpwm_pwm_restore_context()
547 ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); in ehrpwm_pwm_restore_context()
548 ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); in ehrpwm_pwm_restore_context()
549 ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); in ehrpwm_pwm_restore_context()
559 for (i = 0; i < pc->chip.npwm; i++) { in ehrpwm_pwm_suspend()
560 struct pwm_device *pwm = &pc->chip.pwms[i]; in ehrpwm_pwm_suspend() local
562 if (!pwm_is_enabled(pwm)) in ehrpwm_pwm_suspend()
565 /* Disable explicitly if PWM is running */ in ehrpwm_pwm_suspend()
577 for (i = 0; i < pc->chip.npwm; i++) { in ehrpwm_pwm_resume()
578 struct pwm_device *pwm = &pc->chip.pwms[i]; in ehrpwm_pwm_resume() local
580 if (!pwm_is_enabled(pwm)) in ehrpwm_pwm_resume()
583 /* Enable explicitly if PWM was running */ in ehrpwm_pwm_resume()
606 MODULE_DESCRIPTION("EHRPWM PWM driver");