Lines Matching +full:capture +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ member
50 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
61 * Capture using PWM input mode:
83 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
85 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
86 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
90 * - Period = t2 - t0
91 * - Duty cycle = t1 - t0
97 struct device *parent = priv->chip.dev->parent; in stm32_pwm_raw_capture()
102 /* Ensure registers have been updated, enable counter and capture */ in stm32_pwm_raw_capture()
103 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_raw_capture()
104 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_raw_capture()
106 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ in stm32_pwm_raw_capture()
107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; in stm32_pwm_raw_capture()
108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; in stm32_pwm_raw_capture()
109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
110 regmap_set_bits(priv->regmap, TIM_CCER, ccen); in stm32_pwm_raw_capture()
114 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. in stm32_pwm_raw_capture()
115 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } in stm32_pwm_raw_capture()
118 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, in stm32_pwm_raw_capture()
123 /* Period: t2 - t0 (take care of counter overflow) */ in stm32_pwm_raw_capture()
124 if (priv->capture[0] <= priv->capture[2]) in stm32_pwm_raw_capture()
125 *raw_prd = priv->capture[2] - priv->capture[0]; in stm32_pwm_raw_capture()
127 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; in stm32_pwm_raw_capture()
129 /* Duty cycle capture requires at least two capture units */ in stm32_pwm_raw_capture()
130 if (pwm->chip->npwm < 2) in stm32_pwm_raw_capture()
132 else if (priv->capture[0] <= priv->capture[3]) in stm32_pwm_raw_capture()
133 *raw_dty = priv->capture[3] - priv->capture[0]; in stm32_pwm_raw_capture()
135 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; in stm32_pwm_raw_capture()
140 * falling edge triggers new capture on TI2/4 before DMA in stm32_pwm_raw_capture()
141 * had a chance to read CCR2/4. It means capture[1] in stm32_pwm_raw_capture()
144 *raw_dty -= *raw_prd; in stm32_pwm_raw_capture()
148 regmap_clear_bits(priv->regmap, TIM_CCER, ccen); in stm32_pwm_raw_capture()
149 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_raw_capture()
164 mutex_lock(&priv->lock); in stm32_pwm_capture()
167 ret = -EBUSY; in stm32_pwm_capture()
171 ret = clk_enable(priv->clk); in stm32_pwm_capture()
173 dev_err(priv->chip.dev, "failed to enable counter clock\n"); in stm32_pwm_capture()
177 rate = clk_get_rate(priv->clk); in stm32_pwm_capture()
179 ret = -EINVAL; in stm32_pwm_capture()
187 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { in stm32_pwm_capture()
192 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); in stm32_pwm_capture()
193 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
196 regmap_write(priv->regmap, TIM_TISEL, 0x0); in stm32_pwm_capture()
197 regmap_write(priv->regmap, TIM_SMCR, 0x0); in stm32_pwm_capture()
200 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? in stm32_pwm_capture()
206 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ in stm32_pwm_capture()
207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? in stm32_pwm_capture()
208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? in stm32_pwm_capture()
216 * Got a capture. Try to improve accuracy at high rates: in stm32_pwm_capture()
217 * - decrease counter clock prescaler, scale up to max rate. in stm32_pwm_capture()
218 * - use input prescaler, capture once every /2 /4 or /8 edges. in stm32_pwm_capture()
221 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ in stm32_pwm_capture()
225 scale = priv->max_arr; /* bellow resolution, use max scale */ in stm32_pwm_capture()
231 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
244 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) in stm32_pwm_capture()
254 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
267 * capture starts on high side (before falling edge). in stm32_pwm_capture()
268 * Example with icpsc to capture on each 4 events: in stm32_pwm_capture()
270 * start 1st capture 2nd capture in stm32_pwm_capture()
281 * Capture0: .<----------------------------->. in stm32_pwm_capture()
282 * Capture1: .<-------------------------->. . in stm32_pwm_capture()
284 * Period: .<------> . . in stm32_pwm_capture()
288 * - Period = Capture0 / icpsc in stm32_pwm_capture()
289 * - Duty = Period - Low side = Period - (Capture0 - Capture1) in stm32_pwm_capture()
291 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); in stm32_pwm_capture()
296 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); in stm32_pwm_capture()
298 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); in stm32_pwm_capture()
300 regmap_write(priv->regmap, TIM_CCER, 0); in stm32_pwm_capture()
301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); in stm32_pwm_capture()
302 regmap_write(priv->regmap, TIM_PSC, 0); in stm32_pwm_capture()
304 clk_disable(priv->clk); in stm32_pwm_capture()
306 mutex_unlock(&priv->lock); in stm32_pwm_capture()
319 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; in stm32_pwm_config()
324 while (div > priv->max_arr) { in stm32_pwm_config()
333 return -EINVAL; in stm32_pwm_config()
336 * All channels share the same prescaler and counter so when two in stm32_pwm_config()
337 * channels are active at the same time we can't change them in stm32_pwm_config()
342 regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_pwm_config()
343 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_pwm_config()
345 if ((psc != prescaler) || (arr != prd - 1)) in stm32_pwm_config()
346 return -EBUSY; in stm32_pwm_config()
349 regmap_write(priv->regmap, TIM_PSC, prescaler); in stm32_pwm_config()
350 regmap_write(priv->regmap, TIM_ARR, prd - 1); in stm32_pwm_config()
351 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_pwm_config()
357 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty); in stm32_pwm_config()
365 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); in stm32_pwm_config()
367 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); in stm32_pwm_config()
369 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); in stm32_pwm_config()
380 if (priv->have_complementary_output) in stm32_pwm_set_polarity()
383 regmap_update_bits(priv->regmap, TIM_CCER, mask, in stm32_pwm_set_polarity()
394 ret = clk_enable(priv->clk); in stm32_pwm_enable()
400 if (priv->have_complementary_output) in stm32_pwm_enable()
403 regmap_set_bits(priv->regmap, TIM_CCER, mask); in stm32_pwm_enable()
406 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_enable()
409 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_enable()
420 if (priv->have_complementary_output) in stm32_pwm_disable()
423 regmap_clear_bits(priv->regmap, TIM_CCER, mask); in stm32_pwm_disable()
425 /* When all channels are disabled, we can disable the controller */ in stm32_pwm_disable()
427 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_disable()
429 clk_disable(priv->clk); in stm32_pwm_disable()
439 enabled = pwm->state.enabled; in stm32_pwm_apply()
441 if (enabled && !state->enabled) { in stm32_pwm_apply()
442 stm32_pwm_disable(priv, pwm->hwpwm); in stm32_pwm_apply()
446 if (state->polarity != pwm->state.polarity) in stm32_pwm_apply()
447 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); in stm32_pwm_apply()
449 ret = stm32_pwm_config(priv, pwm->hwpwm, in stm32_pwm_apply()
450 state->duty_cycle, state->period); in stm32_pwm_apply()
454 if (!enabled && state->enabled) in stm32_pwm_apply()
455 ret = stm32_pwm_enable(priv, pwm->hwpwm); in stm32_pwm_apply()
466 /* protect common prescaler for all active channels */ in stm32_pwm_apply_locked()
467 mutex_lock(&priv->lock); in stm32_pwm_apply_locked()
469 mutex_unlock(&priv->lock); in stm32_pwm_apply_locked()
478 int ch = pwm->hwpwm; in stm32_pwm_get_state()
484 mutex_lock(&priv->lock); in stm32_pwm_get_state()
486 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_get_state()
490 state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4)); in stm32_pwm_get_state()
491 state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ? in stm32_pwm_get_state()
493 ret = regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_pwm_get_state()
496 ret = regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_pwm_get_state()
499 ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr); in stm32_pwm_get_state()
503 rate = clk_get_rate(priv->clk); in stm32_pwm_get_state()
506 state->period = DIV_ROUND_UP_ULL(prd, rate); in stm32_pwm_get_state()
508 state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); in stm32_pwm_get_state()
511 mutex_unlock(&priv->lock); in stm32_pwm_get_state()
518 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
524 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); in stm32_pwm_set_breakinput()
525 u32 bke = TIM_BDTR_BKE(bi->index); in stm32_pwm_set_breakinput()
526 u32 bkp = TIM_BDTR_BKP(bi->index); in stm32_pwm_set_breakinput()
527 u32 bkf = TIM_BDTR_BKF(bi->index); in stm32_pwm_set_breakinput()
531 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; in stm32_pwm_set_breakinput()
533 if (bi->level) in stm32_pwm_set_breakinput()
536 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); in stm32_pwm_set_breakinput()
538 regmap_read(priv->regmap, TIM_BDTR, &bdtr); in stm32_pwm_set_breakinput()
540 return (bdtr & bke) ? 0 : -EINVAL; in stm32_pwm_set_breakinput()
548 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_apply_breakinputs()
549 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); in stm32_pwm_apply_breakinputs()
574 return -EINVAL; in stm32_pwm_probe_breakinputs()
576 priv->num_breakinputs = nb; in stm32_pwm_probe_breakinputs()
579 (u32 *)priv->breakinputs, array_size); in stm32_pwm_probe_breakinputs()
583 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_probe_breakinputs()
584 if (priv->breakinputs[i].index > 1 || in stm32_pwm_probe_breakinputs()
585 priv->breakinputs[i].level > 1 || in stm32_pwm_probe_breakinputs()
586 priv->breakinputs[i].filter > 15) in stm32_pwm_probe_breakinputs()
587 return -EINVAL; in stm32_pwm_probe_breakinputs()
601 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); in stm32_pwm_detect_complementary()
602 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_detect_complementary()
603 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); in stm32_pwm_detect_complementary()
605 priv->have_complementary_output = (ccer != 0); in stm32_pwm_detect_complementary()
614 * If channels enable bits don't exist writing 1 will have no in stm32_pwm_detect_channels()
617 regmap_read(priv->regmap, TIM_CCER, &ccer_backup); in stm32_pwm_detect_channels()
618 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); in stm32_pwm_detect_channels()
619 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_detect_channels()
620 regmap_write(priv->regmap, TIM_CCER, ccer_backup); in stm32_pwm_detect_channels()
629 struct device *dev = &pdev->dev; in stm32_pwm_probe()
630 struct device_node *np = dev->of_node; in stm32_pwm_probe()
631 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); in stm32_pwm_probe()
639 return -ENOMEM; in stm32_pwm_probe()
641 mutex_init(&priv->lock); in stm32_pwm_probe()
642 priv->regmap = ddata->regmap; in stm32_pwm_probe()
643 priv->clk = ddata->clk; in stm32_pwm_probe()
644 priv->max_arr = ddata->max_arr; in stm32_pwm_probe()
646 if (!priv->regmap || !priv->clk) in stm32_pwm_probe()
647 return -EINVAL; in stm32_pwm_probe()
655 priv->chip.dev = dev; in stm32_pwm_probe()
656 priv->chip.ops = &stm32pwm_ops; in stm32_pwm_probe()
657 priv->chip.npwm = stm32_pwm_detect_channels(priv, &num_enabled); in stm32_pwm_probe()
659 /* Initialize clock refcount to number of enabled PWM channels. */ in stm32_pwm_probe()
661 clk_enable(priv->clk); in stm32_pwm_probe()
663 ret = devm_pwmchip_add(dev, &priv->chip); in stm32_pwm_probe()
678 /* Look for active channels */ in stm32_pwm_suspend()
681 for (i = 0; i < priv->chip.npwm; i++) { in stm32_pwm_suspend()
685 i, priv->chip.pwms[i].label); in stm32_pwm_suspend()
686 return -EBUSY; in stm32_pwm_suspend()
709 { .compatible = "st,stm32-pwm", },
717 .name = "stm32-pwm",
724 MODULE_ALIAS("platform:stm32-pwm");