1 // SPDX-License-Identifier: GPL-2.0
63 	return readl_relaxed(spc->base + offset);  in sprd_pwm_read()
71 	writel_relaxed(val, spc->base + offset);  in sprd_pwm_write()
78 	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];  in sprd_pwm_get_state()
79 	u32 val, duty, prescale;  in sprd_pwm_get_state()  local
87 	ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);  in sprd_pwm_get_state()
89 		dev_err(spc->dev, "failed to enable pwm%u clocks\n",  in sprd_pwm_get_state()
90 			pwm->hwpwm);  in sprd_pwm_get_state()
94 	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);  in sprd_pwm_get_state()
96 		state->enabled = true;  in sprd_pwm_get_state()
98 		state->enabled = false;  in sprd_pwm_get_state()
103 	 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.  in sprd_pwm_get_state()
106 	 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate  in sprd_pwm_get_state()
108 	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);  in sprd_pwm_get_state()
111 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);  in sprd_pwm_get_state()
113 	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);  in sprd_pwm_get_state()
114 	duty = val & SPRD_PWM_DUTY_MSK;  in sprd_pwm_get_state()
115 	tmp = (prescale + 1) * NSEC_PER_SEC * duty;  in sprd_pwm_get_state()
116 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);  in sprd_pwm_get_state()
117 	state->polarity = PWM_POLARITY_NORMAL;  in sprd_pwm_get_state()
120 	if (!state->enabled)  in sprd_pwm_get_state()
121 		clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);  in sprd_pwm_get_state()
129 	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];  in sprd_pwm_config()
130 	u32 prescale, duty;  in sprd_pwm_config()  local
136 	 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.  in sprd_pwm_config()
143 	duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;  in sprd_pwm_config()
145 	tmp = (u64)chn->clk_rate * period_ns;  in sprd_pwm_config()
147 	prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;  in sprd_pwm_config()
152 	 * Note: Writing DUTY triggers the hardware to actually apply the  in sprd_pwm_config()
153 	 * values written to MOD and DUTY to the output, so must keep writing  in sprd_pwm_config()
154 	 * DUTY last.  in sprd_pwm_config()
159 	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);  in sprd_pwm_config()
160 	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);  in sprd_pwm_config()
161 	sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);  in sprd_pwm_config()
170 	struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];  in sprd_pwm_apply()
171 	struct pwm_state *cstate = &pwm->state;  in sprd_pwm_apply()
174 	if (state->polarity != PWM_POLARITY_NORMAL)  in sprd_pwm_apply()
175 		return -EINVAL;  in sprd_pwm_apply()
177 	if (state->enabled) {  in sprd_pwm_apply()
178 		if (!cstate->enabled) {  in sprd_pwm_apply()
184 						      chn->clks);  in sprd_pwm_apply()
186 				dev_err(spc->dev,  in sprd_pwm_apply()
188 					pwm->hwpwm);  in sprd_pwm_apply()
193 		ret = sprd_pwm_config(spc, pwm, state->duty_cycle,  in sprd_pwm_apply()
194 				      state->period);  in sprd_pwm_apply()
198 		sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);  in sprd_pwm_apply()
199 	} else if (cstate->enabled) {  in sprd_pwm_apply()
205 		sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);  in sprd_pwm_apply()
207 		clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);  in sprd_pwm_apply()
224 		struct sprd_pwm_chn *chn = &spc->chn[i];  in sprd_pwm_clk_init()
228 			chn->clks[j].id =  in sprd_pwm_clk_init()
231 		ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,  in sprd_pwm_clk_init()
232 					chn->clks);  in sprd_pwm_clk_init()
234 			if (ret == -ENOENT)  in sprd_pwm_clk_init()
237 			return dev_err_probe(spc->dev, ret,  in sprd_pwm_clk_init()
241 		clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;  in sprd_pwm_clk_init()
242 		chn->clk_rate = clk_get_rate(clk_pwm);  in sprd_pwm_clk_init()
246 		return dev_err_probe(spc->dev, -ENODEV, "no available PWM channels\n");  in sprd_pwm_clk_init()
248 	spc->num_pwms = i;  in sprd_pwm_clk_init()
258 	spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);  in sprd_pwm_probe()
260 		return -ENOMEM;  in sprd_pwm_probe()
262 	spc->base = devm_platform_ioremap_resource(pdev, 0);  in sprd_pwm_probe()
263 	if (IS_ERR(spc->base))  in sprd_pwm_probe()
264 		return PTR_ERR(spc->base);  in sprd_pwm_probe()
266 	spc->dev = &pdev->dev;  in sprd_pwm_probe()
272 	spc->chip.dev = &pdev->dev;  in sprd_pwm_probe()
273 	spc->chip.ops = &sprd_pwm_ops;  in sprd_pwm_probe()
274 	spc->chip.npwm = spc->num_pwms;  in sprd_pwm_probe()
276 	ret = devm_pwmchip_add(&pdev->dev, &spc->chip);  in sprd_pwm_probe()
278 		dev_err(&pdev->dev, "failed to add PWM chip\n");  in sprd_pwm_probe()
284 	{ .compatible = "sprd,ums512-pwm", },
291 		.name = "sprd-pwm",