1 // SPDX-License-Identifier: GPL-2.0
3  * Intel Keem Bay PWM driver
10  * - Upon disabling a channel, the currently running
22 #include <linux/pwm.h>
34 /* PWM Register offset */
72 					   u32 val, u32 offset)  in keembay_pwm_update_bits()  argument
74 	u32 buff = readl(priv->base + offset);  in keembay_pwm_update_bits()
77 	writel(buff, priv->base + offset);  in keembay_pwm_update_bits()
92 static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in keembay_pwm_get_state()  argument
100 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_get_state()
103 	highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
105 		state->enabled = true;  in keembay_pwm_get_state()
107 		state->enabled = false;  in keembay_pwm_get_state()
110 	highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
113 	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);  in keembay_pwm_get_state()
114 	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);  in keembay_pwm_get_state()
115 	state->polarity = PWM_POLARITY_NORMAL;  in keembay_pwm_get_state()
120 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in keembay_pwm_apply()  argument
130 	if (state->polarity != PWM_POLARITY_NORMAL)  in keembay_pwm_apply()
131 		return -EINVAL;  in keembay_pwm_apply()
134 	 * Configure the pwm repeat count as infinite at (15:0) and leadin  in keembay_pwm_apply()
138 				KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
140 	keembay_pwm_get_state(chip, pwm, &current_state);  in keembay_pwm_apply()
142 	if (!state->enabled) {  in keembay_pwm_apply()
144 			keembay_pwm_disable(priv, pwm->hwpwm);  in keembay_pwm_apply()
154 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_apply()
155 	div = clk_rate * state->duty_cycle;  in keembay_pwm_apply()
158 		return -ERANGE;  in keembay_pwm_apply()
161 	div = clk_rate * state->period;  in keembay_pwm_apply()
163 	div = div - high;  in keembay_pwm_apply()
165 		return -ERANGE;  in keembay_pwm_apply()
172 	writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
174 	if (state->enabled && !current_state.enabled)  in keembay_pwm_apply()
175 		keembay_pwm_enable(priv, pwm->hwpwm);  in keembay_pwm_apply()
187 	struct device *dev = &pdev->dev;  in keembay_pwm_probe()
193 		return -ENOMEM;  in keembay_pwm_probe()
195 	priv->clk = devm_clk_get(dev, NULL);  in keembay_pwm_probe()
196 	if (IS_ERR(priv->clk))  in keembay_pwm_probe()
197 		return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");  in keembay_pwm_probe()
199 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in keembay_pwm_probe()
200 	if (IS_ERR(priv->base))  in keembay_pwm_probe()
201 		return PTR_ERR(priv->base);  in keembay_pwm_probe()
203 	ret = keembay_clk_enable(dev, priv->clk);  in keembay_pwm_probe()
207 	priv->chip.dev = dev;  in keembay_pwm_probe()
208 	priv->chip.ops = &keembay_pwm_ops;  in keembay_pwm_probe()
209 	priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;  in keembay_pwm_probe()
211 	ret = devm_pwmchip_add(dev, &priv->chip);  in keembay_pwm_probe()
213 		return dev_err_probe(dev, ret, "Failed to add PWM chip\n");  in keembay_pwm_probe()
219 	{ .compatible = "intel,keembay-pwm" },
227 		.name = "pwm-keembay",
233 MODULE_ALIAS("platform:pwm-keembay");
234 MODULE_DESCRIPTION("Intel Keem Bay PWM driver");