Lines Matching +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <dt-bindings/power/px30-power.h>
24 #include <dt-bindings/power/rockchip,rv1126-power.h>
25 #include <dt-bindings/power/rk3036-power.h>
26 #include <dt-bindings/power/rk3066-power.h>
27 #include <dt-bindings/power/rk3128-power.h>
28 #include <dt-bindings/power/rk3188-power.h>
29 #include <dt-bindings/power/rk3228-power.h>
30 #include <dt-bindings/power/rk3288-power.h>
31 #include <dt-bindings/power/rk3328-power.h>
32 #include <dt-bindings/power/rk3366-power.h>
33 #include <dt-bindings/power/rk3368-power.h>
34 #include <dt-bindings/power/rk3399-power.h>
35 #include <dt-bindings/power/rk3568-power.h>
36 #include <dt-bindings/power/rk3588-power.h>
179 * Dynamic Memory Controller may need to coordinate with us -- see
182 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
213 mutex_lock(&pmu->mutex); in rockchip_pmu_block()
217 * enabled for the duration of power-domain transitions. Most in rockchip_pmu_block()
219 * particular, DRAM DVFS / memory-controller idle) must be handled by in rockchip_pmu_block()
225 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_block()
226 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
229 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pmu_block()
231 dev_err(pmu->dev, in rockchip_pmu_block()
233 genpd->name, ret); in rockchip_pmu_block()
242 for (i = i - 1; i >= 0; i--) { in rockchip_pmu_block()
243 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
246 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_block()
249 mutex_unlock(&pmu->mutex); in rockchip_pmu_block()
266 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_unblock()
267 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_unblock()
270 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_unblock()
274 mutex_unlock(&pmu->mutex); in rockchip_pmu_unblock()
286 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
287 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
290 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
291 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
298 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
305 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
306 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
307 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
308 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
314 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
316 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
317 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
318 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
319 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
321 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
322 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
327 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
329 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
332 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
334 genpd->name, val); in rockchip_pmu_set_idle_request()
341 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
343 genpd->name, is_idle); in rockchip_pmu_set_idle_request()
354 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
355 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
357 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
358 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
360 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
361 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
363 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
364 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
366 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
367 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
369 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
378 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
379 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
381 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
382 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
384 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
385 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
387 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
388 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
390 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
391 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
393 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
401 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
404 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
405 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
407 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
410 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
411 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
414 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
417 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
422 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
425 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
426 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
429 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
434 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
437 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
438 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
441 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
446 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
447 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
454 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
456 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
462 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
463 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
469 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
471 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
475 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
476 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
482 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
484 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
494 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
495 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
496 u32 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
499 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
502 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
505 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
506 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
507 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
508 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
510 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
511 pd->info->pwr_mask, on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
520 dev_err(pmu->dev, in rockchip_do_pmu_set_power_domain()
522 genpd->name, is_on); in rockchip_do_pmu_set_power_domain()
529 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
532 mutex_lock(&pmu->mutex); in rockchip_pd_power()
535 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
537 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
538 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
558 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
561 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
586 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
595 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
612 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
629 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
632 return -EINVAL; in rockchip_pm_add_one_domain()
635 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
636 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
638 return -EINVAL; in rockchip_pm_add_one_domain()
641 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
644 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
646 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
648 return -EINVAL; in rockchip_pm_add_one_domain()
651 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
653 return -ENOMEM; in rockchip_pm_add_one_domain()
655 pd->info = pd_info; in rockchip_pm_add_one_domain()
656 pd->pmu = pmu; in rockchip_pm_add_one_domain()
658 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
659 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
660 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
661 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
662 if (!pd->clks) in rockchip_pm_add_one_domain()
663 return -ENOMEM; in rockchip_pm_add_one_domain()
665 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
666 node, pd->num_clks); in rockchip_pm_add_one_domain()
667 pd->num_clks = 0; in rockchip_pm_add_one_domain()
670 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
671 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
672 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
673 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
674 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
681 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
685 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", in rockchip_pm_add_one_domain()
688 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
689 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
690 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
692 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
693 error = -ENOMEM; in rockchip_pm_add_one_domain()
698 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, in rockchip_pm_add_one_domain()
699 pd->num_qos, in rockchip_pm_add_one_domain()
702 if (!pd->qos_save_regs[j]) { in rockchip_pm_add_one_domain()
703 error = -ENOMEM; in rockchip_pm_add_one_domain()
708 for (j = 0; j < pd->num_qos; j++) { in rockchip_pm_add_one_domain()
711 error = -ENODEV; in rockchip_pm_add_one_domain()
714 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); in rockchip_pm_add_one_domain()
715 if (IS_ERR(pd->qos_regmap[j])) { in rockchip_pm_add_one_domain()
716 error = -ENODEV; in rockchip_pm_add_one_domain()
724 if (pd->info->name) in rockchip_pm_add_one_domain()
725 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
727 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
728 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
729 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
730 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
731 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
732 pd->genpd.flags = GENPD_FLAG_PM_CLK; in rockchip_pm_add_one_domain()
733 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
734 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
735 pm_genpd_init(&pd->genpd, NULL, in rockchip_pm_add_one_domain()
737 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); in rockchip_pm_add_one_domain()
739 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
743 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
745 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
757 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
759 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
760 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
762 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
763 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
765 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
766 mutex_lock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
767 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
768 mutex_unlock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
779 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
780 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
795 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
797 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
812 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
817 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
821 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
828 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
833 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
837 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
838 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
841 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
842 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
857 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
858 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
867 return -ENODEV; in rockchip_pm_domain_probe()
873 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
876 return -ENOMEM; in rockchip_pm_domain_probe()
878 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
879 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
881 pmu->info = pmu_info; in rockchip_pm_domain_probe()
883 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
884 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
886 parent = dev->parent; in rockchip_pm_domain_probe()
889 return -ENODEV; in rockchip_pm_domain_probe()
892 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
893 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
895 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
902 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
903 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
904 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
905 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
906 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
907 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
909 error = -ENODEV; in rockchip_pm_domain_probe()
940 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
961 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
962 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
963 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
964 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
965 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
966 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
967 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
968 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
972 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
973 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
974 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
975 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
976 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
977 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
978 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
979 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
983 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
984 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
985 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
986 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
987 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
988 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
989 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
993 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
994 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
995 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
996 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
997 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1001 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1002 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1003 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1004 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1005 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1009 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1010 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1011 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1012 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1013 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1017 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1018 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1019 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1020 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1021 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1022 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1023 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1024 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1025 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1026 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1027 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1031 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1032 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1033 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1034 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1038 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1039 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1040 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1041 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1042 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1043 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1044 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1045 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1046 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1050 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1051 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1052 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1053 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1054 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1055 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1056 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1060 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1061 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1062 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1063 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1064 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1068 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1069 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1070 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1071 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1072 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1073 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1074 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1075 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1076 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1077 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1078 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1079 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1080 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1081 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1082 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1083 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1084 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1085 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1086 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1087 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1088 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1089 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1090 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1091 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1092 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1093 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1094 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1098 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1099 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1100 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1101 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1102 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1103 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1104 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1105 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1106 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1110 …K3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0…
1111 …[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, …
1112 …[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0…
1113 …588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1…
1114 …K3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2…
1115 …K3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3…
1116 …3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4…
1117 …3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5…
1118 …88_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6…
1119 …88_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7…
1120 …K3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8…
1121 …[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0,…
1122 …K3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9…
1123 …RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(1…
1124 …[RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, …
1125 …K3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(1…
1126 …3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(1…
1127 …OP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(1…
1128 …K3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(1…
1129 …K3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0…
1130 …3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1…
1131 …K3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5…
1132 …[RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, …
1133 …[RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, …
1134 …K3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2…
1135 …[RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, …
1136 …K3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3…
1137 …K3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4…
1138 …[RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0,…
1315 .compatible = "rockchip,px30-power-controller",
1319 .compatible = "rockchip,rk3036-power-controller",
1323 .compatible = "rockchip,rk3066-power-controller",
1327 .compatible = "rockchip,rk3128-power-controller",
1331 .compatible = "rockchip,rk3188-power-controller",
1335 .compatible = "rockchip,rk3228-power-controller",
1339 .compatible = "rockchip,rk3288-power-controller",
1343 .compatible = "rockchip,rk3328-power-controller",
1347 .compatible = "rockchip,rk3366-power-controller",
1351 .compatible = "rockchip,rk3368-power-controller",
1355 .compatible = "rockchip,rk3399-power-controller",
1359 .compatible = "rockchip,rk3568-power-controller",
1363 .compatible = "rockchip,rk3588-power-controller",
1367 .compatible = "rockchip,rv1126-power-controller",
1376 .name = "rockchip-pm-domain",