1 // SPDX-License-Identifier: GPL-2.0+
4  * Copyright 2017-2018 NXP
10  * single global power domain and implement the ->attach|detach_dev()
12  * From within the ->attach_dev(), we could get the OF node for
13  * the device that is being attached and then parse the power-domain
18  * Additionally, we need to implement the ->stop() and ->start()
20  * rather than using the above ->power_on|off() callbacks.
23  * 1. The ->attach_dev() of power domain infrastructure still does
32  *    Update: Genpd assigns the ->of_node for the virtual device before it
33  *    invokes ->attach_dev() callback, hence parsing for device resources via
37  *    behavior changed if removing ->power_on|off() callback and use
38  *    ->start() and ->stop() instead. genpd_dev_pm_attach will only power
54 #include <dt-bindings/firmware/imx/rsrc.h>
56 #include <linux/firmware/imx/sci.h>
57 #include <linux/firmware/imx/svc/rm.h>
145 	{ "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 },
146 	{ "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
147 	{ "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
148 	{ "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
149 	{ "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 },
150 	{ "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 },
151 	{ "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 },
152 	{ "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
153 	{ "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
154 	{ "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 },
155 	{ "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 },
171 	{ "dsp-ram", IMX_SC_R_DSP_RAM, 1, false, 0 },
179 	{ "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 },
180 	{ "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 },
188 	{ "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 },
189 	{ "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 },
190 	{ "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 },
191 	{ "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 },
192 	{ "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 },
193 	{ "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 },
194 	{ "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 },
197 	{ "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
198 	{ "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 },
202 	{ "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 },
203 	{ "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 },
204 	{ "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 },
205 	{ "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 },
206 	{ "sata-0", IMX_SC_R_SATA_0, 1, false, 0 },
207 	{ "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 },
211 	{ "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 },
212 	{ "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 },
215 	{ "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, false, 0 },
216 	{ "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, true, 0 },
220 	{ "lvds0-pwm", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 },
221 	{ "lvds0-lpi2c", IMX_SC_R_LVDS_0_I2C_0, 2, true, 0 },
223 	{ "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 },
224 	{ "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 },
227 	{ "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 },
228 	{ "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 },
233 	{ "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 },
234 	{ "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 },
237 	{ "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 },
238 	{ "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 },
241 	{ "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 },
242 	{ "cm40-intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 },
243 	{ "cm40-pid", IMX_SC_R_M4_0_PID0, 5, true, 0},
244 	{ "cm40-mu-a1", IMX_SC_R_M4_0_MU_1A, 1, false, 0},
245 	{ "cm40-lpuart", IMX_SC_R_M4_0_UART, 1, false, 0},
248 	{ "cm41-i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 },
249 	{ "cm41-intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 },
250 	{ "cm41-pid", IMX_SC_R_M4_1_PID0, 5, true, 0},
251 	{ "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0},
252 	{ "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0},
262 	{ "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 },
263 	{ "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 },
264 	{ "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 },
265 	{ "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 },
274 	{ "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 },
275 	{ "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 },
276 	{ "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 },
277 	{ "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 },
278 	{ "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 },
279 	{ "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 },
280 	{ "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 },
281 	{ "img-parallel", IMX_SC_R_PI_0, 1, false, 0 },
282 	{ "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 },
283 	{ "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 },
284 	{ "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 },
287 	{ "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0},
288 	{ "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0},
289 	{ "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0},
290 	{ "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0},
291 	{ "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0},
294 	{ "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0},
295 	{ "hdmi-rx-pwm", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0},
296 	{ "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0},
297 	{ "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0},
300 	{ "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2},
327 	ret = of_parse_phandle_with_args(of_stdout, "power-domains",  in imx_sc_pd_get_console_rsrc()
328 					 "#power-domain-cells",  in imx_sc_pd_get_console_rsrc()
342 	hdr->ver = IMX_SC_RPC_VERSION;  in imx_sc_get_pd_power()
343 	hdr->svc = IMX_SC_RPC_SVC_PM;  in imx_sc_get_pd_power()
344 	hdr->func = IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE;  in imx_sc_get_pd_power()
345 	hdr->size = 2;  in imx_sc_get_pd_power()
366 	hdr->ver = IMX_SC_RPC_VERSION;  in imx_sc_pd_power()
367 	hdr->svc = IMX_SC_RPC_SVC_PM;  in imx_sc_pd_power()
368 	hdr->func = IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE;  in imx_sc_pd_power()
369 	hdr->size = 2;  in imx_sc_pd_power()
371 	msg.resource = pd->rsrc;  in imx_sc_pd_power()
375 	if (imx_con_rsrc == pd->rsrc && !console_suspend_enabled && !power_on)  in imx_sc_pd_power()
376 		return -EBUSY;  in imx_sc_pd_power()
380 		dev_err(&domain->dev, "failed to power %s resource %d ret %d\n",  in imx_sc_pd_power()
381 			power_on ? "up" : "off", pd->rsrc, ret);  in imx_sc_pd_power()
399 	struct generic_pm_domain *domain = ERR_PTR(-ENOENT);  in imx_scu_pd_xlate()
403 	for (i = 0; i < pd_data->num_domains; i++) {  in imx_scu_pd_xlate()
406 		sc_pd = to_imx_sc_pd(pd_data->domains[i]);  in imx_scu_pd_xlate()
407 		if (sc_pd->rsrc == spec->args[0]) {  in imx_scu_pd_xlate()
408 			domain = &sc_pd->pd;  in imx_scu_pd_xlate()
424 	if (!imx_sc_rm_is_resource_owned(pm_ipc_handle, pd_ranges->rsrc + idx))  in imx_scu_add_pm_domain()
429 		return ERR_PTR(-ENOMEM);  in imx_scu_add_pm_domain()
431 	sc_pd->rsrc = pd_ranges->rsrc + idx;  in imx_scu_add_pm_domain()
432 	sc_pd->pd.power_off = imx_sc_pd_power_off;  in imx_scu_add_pm_domain()
433 	sc_pd->pd.power_on = imx_sc_pd_power_on;  in imx_scu_add_pm_domain()
435 	if (pd_ranges->postfix)  in imx_scu_add_pm_domain()
436 		snprintf(sc_pd->name, sizeof(sc_pd->name),  in imx_scu_add_pm_domain()
437 			 "%s%i", pd_ranges->name, pd_ranges->start_from + idx);  in imx_scu_add_pm_domain()
439 		snprintf(sc_pd->name, sizeof(sc_pd->name),  in imx_scu_add_pm_domain()
440 			 "%s", pd_ranges->name);  in imx_scu_add_pm_domain()
442 	sc_pd->pd.name = sc_pd->name;  in imx_scu_add_pm_domain()
443 	if (imx_con_rsrc == sc_pd->rsrc)  in imx_scu_add_pm_domain()
444 		sc_pd->pd.flags = GENPD_FLAG_RPM_ALWAYS_ON;  in imx_scu_add_pm_domain()
446 	mode = imx_sc_get_pd_power(dev, pd_ranges->rsrc + idx);  in imx_scu_add_pm_domain()
452 	dev_dbg(dev, "%s : %s\n", sc_pd->name, imx_sc_pm_mode[mode]);  in imx_scu_add_pm_domain()
454 	if (sc_pd->rsrc >= IMX_SC_R_LAST) {  in imx_scu_add_pm_domain()
456 			 sc_pd->name, sc_pd->rsrc);  in imx_scu_add_pm_domain()
462 	ret = pm_genpd_init(&sc_pd->pd, NULL, is_off);  in imx_scu_add_pm_domain()
465 			 sc_pd->name, sc_pd->rsrc);  in imx_scu_add_pm_domain()
476 	const struct imx_sc_pd_range *pd_ranges = pd_soc->pd_ranges;  in imx_scu_init_pm_domains()
483 	for (i = 0; i < pd_soc->num_ranges; i++)  in imx_scu_init_pm_domains()
488 		return -ENOMEM;  in imx_scu_init_pm_domains()
492 		return -ENOMEM;  in imx_scu_init_pm_domains()
495 	for (i = 0; i < pd_soc->num_ranges; i++) {  in imx_scu_init_pm_domains()
501 			domains[count++] = &sc_pd->pd;  in imx_scu_init_pm_domains()
502 			dev_dbg(dev, "added power domain %s\n", sc_pd->pd.name);  in imx_scu_init_pm_domains()
506 	pd_data->domains = domains;  in imx_scu_init_pm_domains()
507 	pd_data->num_domains = count;  in imx_scu_init_pm_domains()
508 	pd_data->xlate = imx_scu_pd_xlate;  in imx_scu_init_pm_domains()
510 	of_genpd_add_provider_onecell(dev->of_node, pd_data);  in imx_scu_init_pm_domains()
524 	pd_soc = of_device_get_match_data(&pdev->dev);  in imx_sc_pd_probe()
526 		return -ENODEV;  in imx_sc_pd_probe()
530 	return imx_scu_init_pm_domains(&pdev->dev, pd_soc);  in imx_sc_pd_probe()
534 	{ .compatible = "fsl,imx8qxp-scu-pd", &imx8qxp_scu_pd},
535 	{ .compatible = "fsl,scu-pd", &imx8qxp_scu_pd},
541 		.name = "imx-scu-pd",
550 MODULE_DESCRIPTION("IMX SCU Power Domain driver");