Lines Matching full:bit
74 {"PMC_PGD0_PG_STS", BIT(0)},
75 {"FUSE_OSSE_PGD0_PG_STS", BIT(1)},
76 {"ESPISPI_PGD0_PG_STS", BIT(2)},
77 {"XHCI_PGD0_PG_STS", BIT(3)},
78 {"SPA_PGD0_PG_STS", BIT(4)},
79 {"SPB_PGD0_PG_STS", BIT(5)},
80 {"SPR16B0_PGD0_PG_STS", BIT(6)},
81 {"GBE_PGD0_PG_STS", BIT(7)},
82 {"SBR8B7_PGD0_PG_STS", BIT(8)},
83 {"SBR8B6_PGD0_PG_STS", BIT(9)},
84 {"SBR16B1_PGD0_PG_STS", BIT(10)},
85 {"SBR8B8_PGD0_PG_STS", BIT(11)},
86 {"ESE_PGD3_PG_STS", BIT(12)},
87 {"D2D_DISP_PGD0_PG_STS", BIT(13)},
88 {"LPSS_PGD0_PG_STS", BIT(14)},
89 {"LPC_PGD0_PG_STS", BIT(15)},
90 {"SMB_PGD0_PG_STS", BIT(16)},
91 {"ISH_PGD0_PG_STS", BIT(17)},
92 {"SBR8B2_PGD0_PG_STS", BIT(18)},
93 {"NPK_PGD0_PG_STS", BIT(19)},
94 {"D2D_NOC_PGD0_PG_STS", BIT(20)},
95 {"SAFSS_PGD0_PG_STS", BIT(21)},
96 {"FUSE_PGD0_PG_STS", BIT(22)},
97 {"D2D_DISP_PGD1_PG_STS", BIT(23)},
98 {"MPFPW1_PGD0_PG_STS", BIT(24)},
99 {"XDCI_PGD0_PG_STS", BIT(25)},
100 {"EXI_PGD0_PG_STS", BIT(26)},
101 {"CSE_PGD0_PG_STS", BIT(27)},
102 {"KVMCC_PGD0_PG_STS", BIT(28)},
103 {"PMT_PGD0_PG_STS", BIT(29)},
104 {"CLINK_PGD0_PG_STS", BIT(30)},
105 {"PTIO_PGD0_PG_STS", BIT(31)},
110 {"USBR0_PGD0_PG_STS", BIT(0)},
111 {"SUSRAM_PGD0_PG_STS", BIT(1)},
112 {"SMT1_PGD0_PG_STS", BIT(2)},
113 {"U3FPW1_PGD0_PG_STS", BIT(3)},
114 {"SMS2_PGD0_PG_STS", BIT(4)},
115 {"SMS1_PGD0_PG_STS", BIT(5)},
116 {"CSMERTC_PGD0_PG_STS", BIT(6)},
117 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
118 {"FIA_PG_PGD0_PG_STS", BIT(8)},
119 {"SBR16B4_PGD0_PG_STS", BIT(9)},
120 {"P2SB8B_PGD0_PG_STS", BIT(10)},
121 {"DBG_SBR_PGD0_PG_STS", BIT(11)},
122 {"SBR8B9_PGD0_PG_STS", BIT(12)},
123 {"OSSE_SMT1_PGD0_PG_STS", BIT(13)},
124 {"SBR8B10_PGD0_PG_STS", BIT(14)},
125 {"SBR16B3_PGD0_PG_STS", BIT(15)},
126 {"G5FPW1_PGD0_PG_STS", BIT(16)},
127 {"SBRG_PGD0_PG_STS", BIT(17)},
128 {"PSF4_PGD0_PG_STS", BIT(18)},
129 {"CNVI_PGD0_PG_STS", BIT(19)},
130 {"USFX2_PGD0_PG_STS", BIT(20)},
131 {"ENDBG_PGD0_PG_STS", BIT(21)},
132 {"FIACPCB_P5X4_PGD0_PG_STS", BIT(22)},
133 {"SBR8B3_PGD0_PG_STS", BIT(23)},
134 {"SBR8B0_PGD0_PG_STS", BIT(24)},
135 {"NPK_PGD1_PG_STS", BIT(25)},
136 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(26)},
137 {"D2D_NOC_PGD2_PG_STS", BIT(27)},
138 {"SBR8B1_PGD0_PG_STS", BIT(28)},
139 {"PSF6_PGD0_PG_STS", BIT(29)},
140 {"PSF7_PGD0_PG_STS", BIT(30)},
141 {"FIA_U_PGD0_PG_STS", BIT(31)},
146 {"PSF8_PGD0_PG_STS", BIT(0)},
147 {"SBR16B2_PGD0_PG_STS", BIT(1)},
148 {"D2D_IPU_PGD0_PG_STS", BIT(2)},
149 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
150 {"TAM_PGD0_PG_STS", BIT(4)},
151 {"D2D_NOC_PGD1_PG_STS", BIT(5)},
152 {"TBTLSX_PGD0_PG_STS", BIT(6)},
153 {"THC0_PGD0_PG_STS", BIT(7)},
154 {"THC1_PGD0_PG_STS", BIT(8)},
155 {"PMC_PGD0_PG_STS", BIT(9)},
156 {"SBR8B5_PGD0_PG_STS", BIT(10)},
157 {"UFSPW1_PGD0_PG_STS", BIT(11)},
158 {"DBC_PGD0_PG_STS", BIT(12)},
159 {"TCSS_PGD0_PG_STS", BIT(13)},
160 {"FIA_P5X4_PGD0_PG_STS", BIT(14)},
161 {"DISP_PGA_PGD0_PG_STS", BIT(15)},
162 {"DISP_PSF_PGD0_PG_STS", BIT(16)},
163 {"PSF0_PGD0_PG_STS", BIT(17)},
164 {"P2SB16B_PGD0_PG_STS", BIT(18)},
165 {"ACE_PGD0_PG_STS", BIT(19)},
166 {"ACE_PGD1_PG_STS", BIT(20)},
167 {"ACE_PGD2_PG_STS", BIT(21)},
168 {"ACE_PGD3_PG_STS", BIT(22)},
169 {"ACE_PGD4_PG_STS", BIT(23)},
170 {"ACE_PGD5_PG_STS", BIT(24)},
171 {"ACE_PGD6_PG_STS", BIT(25)},
172 {"ACE_PGD7_PG_STS", BIT(26)},
173 {"ACE_PGD8_PG_STS", BIT(27)},
174 {"ACE_PGD9_PG_STS", BIT(28)},
175 {"ACE_PGD10_PG_STS", BIT(29)},
176 {"FIACPCB_PG_PGD0_PG_STS", BIT(30)},
177 {"OSSE_PGD0_PG_STS", BIT(31)},
182 {"LPSS_D3_STS", BIT(3)},
183 {"XDCI_D3_STS", BIT(4)},
184 {"XHCI_D3_STS", BIT(5)},
185 {"SPA_D3_STS", BIT(12)},
186 {"SPB_D3_STS", BIT(13)},
187 {"OSSE_D3_STS", BIT(15)},
188 {"ESPISPI_D3_STS", BIT(18)},
189 {"PSTH_D3_STS", BIT(21)},
194 {"OSSE_SMT1_D3_STS", BIT(7)},
195 {"GBE_D3_STS", BIT(19)},
196 {"ITSS_D3_STS", BIT(23)},
197 {"CNVI_D3_STS", BIT(27)},
198 {"UFSX2_D3_STS", BIT(28)},
199 {"OSSE_HOTHAM_D3_STS", BIT(31)},
204 {"ESE_D3_STS", BIT(0)},
205 {"CSMERTC_D3_STS", BIT(1)},
206 {"SUSRAM_D3_STS", BIT(2)},
207 {"CSE_D3_STS", BIT(4)},
208 {"KVMCC_D3_STS", BIT(5)},
209 {"USBR0_D3_STS", BIT(6)},
210 {"ISH_D3_STS", BIT(7)},
211 {"SMT1_D3_STS", BIT(8)},
212 {"SMT2_D3_STS", BIT(9)},
213 {"SMT3_D3_STS", BIT(10)},
214 {"OSSE_SMT2_D3_STS", BIT(13)},
215 {"CLINK_D3_STS", BIT(14)},
216 {"PTIO_D3_STS", BIT(16)},
217 {"PMT_D3_STS", BIT(17)},
218 {"SMS1_D3_STS", BIT(18)},
219 {"SMS2_D3_STS", BIT(19)},
224 {"THC0_D3_STS", BIT(14)},
225 {"THC1_D3_STS", BIT(15)},
226 {"OSSE_SMT3_D3_STS", BIT(21)},
227 {"ACE_D3_STS", BIT(23)},
232 {"LPSS_VNN_REQ_STS", BIT(3)},
233 {"OSSE_VNN_REQ_STS", BIT(15)},
234 {"ESPISPI_VNN_REQ_STS", BIT(18)},
239 {"NPK_VNN_REQ_STS", BIT(4)},
240 {"OSSE_SMT1_VNN_REQ_STS", BIT(7)},
241 {"DFXAGG_VNN_REQ_STS", BIT(8)},
242 {"EXI_VNN_REQ_STS", BIT(9)},
243 {"P2D_VNN_REQ_STS", BIT(18)},
244 {"GBE_VNN_REQ_STS", BIT(19)},
245 {"SMB_VNN_REQ_STS", BIT(25)},
246 {"LPC_VNN_REQ_STS", BIT(26)},
251 {"eSE_VNN_REQ_STS", BIT(0)},
252 {"CSMERTC_VNN_REQ_STS", BIT(1)},
253 {"CSE_VNN_REQ_STS", BIT(4)},
254 {"ISH_VNN_REQ_STS", BIT(7)},
255 {"SMT1_VNN_REQ_STS", BIT(8)},
256 {"CLINK_VNN_REQ_STS", BIT(14)},
257 {"SMS1_VNN_REQ_STS", BIT(18)},
258 {"SMS2_VNN_REQ_STS", BIT(19)},
259 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
260 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
261 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
262 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
263 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
268 {"DISP_SHIM_VNN_REQ_STS", BIT(2)},
269 {"DTS0_VNN_REQ_STS", BIT(7)},
270 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
275 {"CPU_C10_REQ_STS", BIT(0)},
276 {"TS_OFF_REQ_STS", BIT(1)},
277 {"PNDE_MET_REQ_STS", BIT(2)},
278 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
279 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},
280 {"NPK_VNNAON_REQ_STS", BIT(5)},
281 {"VNN_SOC_REQ_STS", BIT(6)},
282 {"ISH_VNNAON_REQ_STS", BIT(7)},
283 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8)},
284 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9)},
285 {"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10)},
286 {"PLT_GREATER_REQ_STS", BIT(11)},
287 {"PCIE_CLKREQ_REQ_STS", BIT(12)},
288 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
289 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
290 {"EA_REQ_STS", BIT(15)},
291 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},
292 {"BRK_EV_EN_REQ_STS", BIT(17)},
293 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
294 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
295 {"LPC_CLK_SRC_REQ_STS", BIT(20)},
296 {"ARC_IDLE_REQ_STS", BIT(21)},
297 {"MPHY_SUS_REQ_STS", BIT(22)},
298 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
299 {"UXD_CONNECTED_REQ_STS", BIT(24)},
300 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
301 {"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26)},
302 {"PRE_WAKE0_REQ_STS", BIT(27)},
303 {"PRE_WAKE1_REQ_STS", BIT(28)},
304 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
305 {"WOV_REQ_STS", BIT(30)},
306 {"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31)},
311 {"AON2_OFF_STS", BIT(0)},
312 {"AON3_OFF_STS", BIT(1)},
313 {"AON4_OFF_STS", BIT(2)},
314 {"AON5_OFF_STS", BIT(3)},
315 {"AON1_OFF_STS", BIT(4)},
316 {"MPFPW1_0_PLL_OFF_STS", BIT(6)},
317 {"USB3_PLL_OFF_STS", BIT(8)},
318 {"AON3_SPL_OFF_STS", BIT(9)},
319 {"G5FPW1_PLL_OFF_STS", BIT(15)},
320 {"XTAL_AGGR_OFF_STS", BIT(17)},
321 {"USB2_PLL_OFF_STS", BIT(18)},
322 {"SAF_PLL_OFF_STS", BIT(19)},
323 {"SE_TCSS_PLL_OFF_STS", BIT(20)},
324 {"DDI_PLL_OFF_STS", BIT(21)},
325 {"FILTER_PLL_OFF_STS", BIT(22)},
326 {"ACE_PLL_OFF_STS", BIT(24)},
327 {"FABRIC_PLL_OFF_STS", BIT(25)},
328 {"SOC_PLL_OFF_STS", BIT(26)},
329 {"REF_OFF_STS", BIT(28)},
330 {"IMG_OFF_STS", BIT(29)},
331 {"RTC_PLL_OFF_STS", BIT(31)},
354 {"PMC_0", BIT(0)},
355 {"FUSE_OSSE", BIT(1)},
356 {"ESPISPI", BIT(2)},
357 {"XHCI", BIT(3)},
358 {"SPA", BIT(4)},
359 {"SPB", BIT(5)},
360 {"SBR16B0", BIT(6)},
361 {"GBE", BIT(7)},
363 {"SBR8B7", BIT(0)},
364 {"SBR8B6", BIT(1)},
365 {"SBR16B1", BIT(1)},
366 {"SBR8B8", BIT(2)},
367 {"ESE", BIT(3)},
368 {"SBR8B10", BIT(4)},
369 {"D2D_DISP_0", BIT(5)},
370 {"LPSS", BIT(6)},
371 {"LPC", BIT(7)},
373 {"SMB", BIT(0)},
374 {"ISH", BIT(1)},
375 {"SBR8B2", BIT(2)},
376 {"NPK_0", BIT(3)},
377 {"D2D_NOC_0", BIT(4)},
378 {"SAFSS", BIT(5)},
379 {"FUSE", BIT(6)},
380 {"D2D_DISP_1", BIT(7)},
382 {"MPFPW1", BIT(0)},
383 {"XDCI", BIT(1)},
384 {"EXI", BIT(2)},
385 {"CSE", BIT(3)},
386 {"KVMCC", BIT(4)},
387 {"PMT", BIT(5)},
388 {"CLINK", BIT(6)},
389 {"PTIO", BIT(7)},
391 {"USBR", BIT(0)},
392 {"SUSRAM", BIT(1)},
393 {"SMT1", BIT(2)},
394 {"U3FPW1", BIT(3)},
395 {"SMS2", BIT(4)},
396 {"SMS1", BIT(5)},
397 {"CSMERTC", BIT(6)},
398 {"CSMEPSF", BIT(7)},
400 {"FIA_PG", BIT(0)},
401 {"SBR16B4", BIT(1)},
402 {"P2SB8B", BIT(2)},
403 {"DBG_SBR", BIT(3)},
404 {"SBR8B9", BIT(4)},
405 {"OSSE_SMT1", BIT(5)},
406 {"SBR8B10", BIT(6)},
407 {"SBR16B3", BIT(7)},
409 {"G5FPW1", BIT(0)},
410 {"SBRG", BIT(1)},
411 {"PSF4", BIT(2)},
412 {"CNVI", BIT(3)},
413 {"UFSX2", BIT(4)},
414 {"ENDBG", BIT(5)},
415 {"FIACPCB_P5X4", BIT(6)},
416 {"SBR8B3", BIT(7)},
418 {"SBR8B0", BIT(0)},
419 {"NPK_1", BIT(1)},
420 {"OSSE_HOTHAM", BIT(2)},
421 {"D2D_NOC_2", BIT(3)},
422 {"SBR8B1", BIT(4)},
423 {"PSF6", BIT(5)},
424 {"PSF7", BIT(6)},
425 {"FIA_U", BIT(7)},
427 {"PSF8", BIT(0)},
428 {"SBR16B2", BIT(1)},
429 {"D2D_IPU", BIT(2)},
430 {"FIACPCB_U", BIT(3)},
431 {"TAM", BIT(4)},
432 {"D2D_NOC_1", BIT(5)},
433 {"TBTLSX", BIT(6)},
434 {"THC0", BIT(7)},
436 {"THC1", BIT(0)},
437 {"PMC_1", BIT(1)},
438 {"SBR8B5", BIT(2)},
439 {"UFSPW1", BIT(3)},
440 {"DBC", BIT(4)},
441 {"TCSS", BIT(5)},
442 {"FIA_P5X4", BIT(6)},
443 {"DISP_PGA", BIT(7)},
445 {"DBG_PSF", BIT(0)},
446 {"PSF0", BIT(1)},
447 {"P2SB16B", BIT(2)},
448 {"ACE0", BIT(3)},
449 {"ACE1", BIT(4)},
450 {"ACE2", BIT(5)},
451 {"ACE3", BIT(6)},
452 {"ACE4", BIT(7)},
454 {"ACE5", BIT(0)},
455 {"ACE6", BIT(1)},
456 {"ACE7", BIT(2)},
457 {"ACE8", BIT(3)},
458 {"ACE9", BIT(4)},
459 {"ACE10", BIT(5)},
460 {"FIACPCB", BIT(6)},
461 {"OSSE", BIT(7)},