Lines Matching +full:bank +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2009-2011 ST-Ericsson AB
27 #include "../pinctrl-utils.h"
28 #include "pinctrl-tegra.h"
30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) in pmx_readl() argument
32 return readl(pmx->regs[bank] + reg); in pmx_readl()
35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) in pmx_writel() argument
37 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
39 pmx_readl(pmx, bank, reg); in pmx_writel()
46 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
54 return pmx->soc->groups[group].name; in tegra_pinctrl_get_group_name()
64 *pins = pmx->soc->groups[group].pins; in tegra_pinctrl_get_group_pins()
65 *num_pins = pmx->soc->groups[group].npins; in tegra_pinctrl_get_group_pins()
75 seq_printf(s, " %s", dev_name(pctldev->dev)); in tegra_pinctrl_pin_dbg_show()
85 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
86 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
88 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
89 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
90 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
91 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
93 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
94 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
95 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
96 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
97 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
98 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
107 struct device *dev = pctldev->dev; in tegra_pinctrl_dt_subnode_to_map()
121 if (ret != -EINVAL) in tegra_pinctrl_dt_subnode_to_map()
136 } else if (ret != -EINVAL) { in tegra_pinctrl_dt_subnode_to_map()
227 return pmx->soc->nfunctions; in tegra_pinctrl_get_funcs_count()
235 return pmx->functions[function].name; in tegra_pinctrl_get_func_name()
245 *groups = pmx->functions[function].groups; in tegra_pinctrl_get_func_groups()
246 *num_groups = pmx->functions[function].ngroups; in tegra_pinctrl_get_func_groups()
260 g = &pmx->soc->groups[group]; in tegra_pinctrl_set_mux()
262 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
263 return -EINVAL; in tegra_pinctrl_set_mux()
265 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { in tegra_pinctrl_set_mux()
266 if (g->funcs[i] == function) in tegra_pinctrl_set_mux()
269 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) in tegra_pinctrl_set_mux()
270 return -EINVAL; in tegra_pinctrl_set_mux()
272 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
273 val &= ~(0x3 << g->mux_bit); in tegra_pinctrl_set_mux()
274 val |= i << g->mux_bit; in tegra_pinctrl_set_mux()
275 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
288 for (group = 0; group < pmx->soc->ngroups; ++group) { in tegra_pinctrl_get_group()
294 return &pmx->soc->groups[group]; in tegra_pinctrl_get_group()
298 dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); in tegra_pinctrl_get_group()
310 if (!pmx->soc->sfsel_in_mux) in tegra_pinctrl_gpio_request_enable()
316 return -EINVAL; in tegra_pinctrl_gpio_request_enable()
318 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_request_enable()
319 return -EINVAL; in tegra_pinctrl_gpio_request_enable()
321 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
322 value &= ~BIT(group->sfsel_bit); in tegra_pinctrl_gpio_request_enable()
323 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
336 if (!pmx->soc->sfsel_in_mux) in tegra_pinctrl_gpio_disable_free()
344 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_disable_free()
347 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
348 value |= BIT(group->sfsel_bit); in tegra_pinctrl_gpio_disable_free()
349 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
365 s8 *bank, s32 *reg, s8 *bit, s8 *width) in tegra_pinconf_reg() argument
369 *bank = g->pupd_bank; in tegra_pinconf_reg()
370 *reg = g->pupd_reg; in tegra_pinconf_reg()
371 *bit = g->pupd_bit; in tegra_pinconf_reg()
372 *width = 2; in tegra_pinconf_reg()
375 *bank = g->tri_bank; in tegra_pinconf_reg()
376 *reg = g->tri_reg; in tegra_pinconf_reg()
377 *bit = g->tri_bit; in tegra_pinconf_reg()
378 *width = 1; in tegra_pinconf_reg()
381 *bank = g->mux_bank; in tegra_pinconf_reg()
382 *reg = g->mux_reg; in tegra_pinconf_reg()
383 *bit = g->einput_bit; in tegra_pinconf_reg()
384 *width = 1; in tegra_pinconf_reg()
387 *bank = g->mux_bank; in tegra_pinconf_reg()
388 *reg = g->mux_reg; in tegra_pinconf_reg()
389 *bit = g->odrain_bit; in tegra_pinconf_reg()
390 *width = 1; in tegra_pinconf_reg()
393 *bank = g->mux_bank; in tegra_pinconf_reg()
394 *reg = g->mux_reg; in tegra_pinconf_reg()
395 *bit = g->lock_bit; in tegra_pinconf_reg()
396 *width = 1; in tegra_pinconf_reg()
399 *bank = g->mux_bank; in tegra_pinconf_reg()
400 *reg = g->mux_reg; in tegra_pinconf_reg()
401 *bit = g->ioreset_bit; in tegra_pinconf_reg()
402 *width = 1; in tegra_pinconf_reg()
405 *bank = g->mux_bank; in tegra_pinconf_reg()
406 *reg = g->mux_reg; in tegra_pinconf_reg()
407 *bit = g->rcv_sel_bit; in tegra_pinconf_reg()
408 *width = 1; in tegra_pinconf_reg()
411 if (pmx->soc->hsm_in_mux) { in tegra_pinconf_reg()
412 *bank = g->mux_bank; in tegra_pinconf_reg()
413 *reg = g->mux_reg; in tegra_pinconf_reg()
415 *bank = g->drv_bank; in tegra_pinconf_reg()
416 *reg = g->drv_reg; in tegra_pinconf_reg()
418 *bit = g->hsm_bit; in tegra_pinconf_reg()
419 *width = 1; in tegra_pinconf_reg()
422 if (pmx->soc->schmitt_in_mux) { in tegra_pinconf_reg()
423 *bank = g->mux_bank; in tegra_pinconf_reg()
424 *reg = g->mux_reg; in tegra_pinconf_reg()
426 *bank = g->drv_bank; in tegra_pinconf_reg()
427 *reg = g->drv_reg; in tegra_pinconf_reg()
429 *bit = g->schmitt_bit; in tegra_pinconf_reg()
430 *width = 1; in tegra_pinconf_reg()
433 *bank = g->drv_bank; in tegra_pinconf_reg()
434 *reg = g->drv_reg; in tegra_pinconf_reg()
435 *bit = g->lpmd_bit; in tegra_pinconf_reg()
436 *width = 2; in tegra_pinconf_reg()
439 *bank = g->drv_bank; in tegra_pinconf_reg()
440 *reg = g->drv_reg; in tegra_pinconf_reg()
441 *bit = g->drvdn_bit; in tegra_pinconf_reg()
442 *width = g->drvdn_width; in tegra_pinconf_reg()
445 *bank = g->drv_bank; in tegra_pinconf_reg()
446 *reg = g->drv_reg; in tegra_pinconf_reg()
447 *bit = g->drvup_bit; in tegra_pinconf_reg()
448 *width = g->drvup_width; in tegra_pinconf_reg()
451 *bank = g->drv_bank; in tegra_pinconf_reg()
452 *reg = g->drv_reg; in tegra_pinconf_reg()
453 *bit = g->slwf_bit; in tegra_pinconf_reg()
454 *width = g->slwf_width; in tegra_pinconf_reg()
457 *bank = g->drv_bank; in tegra_pinconf_reg()
458 *reg = g->drv_reg; in tegra_pinconf_reg()
459 *bit = g->slwr_bit; in tegra_pinconf_reg()
460 *width = g->slwr_width; in tegra_pinconf_reg()
463 if (pmx->soc->drvtype_in_mux) { in tegra_pinconf_reg()
464 *bank = g->mux_bank; in tegra_pinconf_reg()
465 *reg = g->mux_reg; in tegra_pinconf_reg()
467 *bank = g->drv_bank; in tegra_pinconf_reg()
468 *reg = g->drv_reg; in tegra_pinconf_reg()
470 *bit = g->drvtype_bit; in tegra_pinconf_reg()
471 *width = 2; in tegra_pinconf_reg()
474 dev_err(pmx->dev, "Invalid config param %04x\n", param); in tegra_pinconf_reg()
475 return -ENOTSUPP; in tegra_pinconf_reg()
490 dev_err(pmx->dev, in tegra_pinconf_reg()
492 param, prop, g->name); in tegra_pinconf_reg()
494 return -ENOTSUPP; in tegra_pinconf_reg()
503 dev_err(pctldev->dev, "pin_config_get op not supported\n"); in tegra_pinconf_get()
504 return -ENOTSUPP; in tegra_pinconf_get()
511 dev_err(pctldev->dev, "pin_config_set op not supported\n"); in tegra_pinconf_set()
512 return -ENOTSUPP; in tegra_pinconf_set()
523 s8 bank, bit, width; in tegra_pinconf_group_get() local
527 g = &pmx->soc->groups[group]; in tegra_pinconf_group_get()
529 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, in tegra_pinconf_group_get()
530 &width); in tegra_pinconf_group_get()
534 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_get()
535 mask = (1 << width) - 1; in tegra_pinconf_group_get()
552 s8 bank, bit, width; in tegra_pinconf_group_set() local
556 g = &pmx->soc->groups[group]; in tegra_pinconf_group_set()
562 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, in tegra_pinconf_group_set()
563 &width); in tegra_pinconf_group_set()
567 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_set()
572 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); in tegra_pinconf_group_set()
573 return -EINVAL; in tegra_pinconf_group_set()
577 /* Special-case Boolean values; allow any non-zero as true */ in tegra_pinconf_group_set()
578 if (width == 1) in tegra_pinconf_group_set()
581 /* Range-check user-supplied value */ in tegra_pinconf_group_set()
582 mask = (1 << width) - 1; in tegra_pinconf_group_set()
584 dev_err(pctldev->dev, in tegra_pinconf_group_set()
586 configs[i], arg, width); in tegra_pinconf_group_set()
587 return -EINVAL; in tegra_pinconf_group_set()
593 pmx_writel(pmx, val, bank, reg); in tegra_pinconf_group_set()
620 s8 bank, bit, width; in tegra_pinconf_group_dbg_show() local
624 g = &pmx->soc->groups[group]; in tegra_pinconf_group_dbg_show()
628 &bank, ®, &bit, &width); in tegra_pinconf_group_dbg_show()
632 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_dbg_show()
634 val &= (1 << width) - 1; in tegra_pinconf_group_dbg_show()
640 if (g->mux_reg >= 0) { in tegra_pinconf_group_dbg_show()
642 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinconf_group_dbg_show()
643 val = g->funcs[(val >> g->mux_bit) & 0x3]; in tegra_pinconf_group_dbg_show()
645 seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name); in tegra_pinconf_group_dbg_show()
687 for (i = 0; i < pmx->soc->ngroups; ++i) { in tegra_pinctrl_clear_parked_bits()
688 g = &pmx->soc->groups[i]; in tegra_pinctrl_clear_parked_bits()
689 if (g->parked_bitmask > 0) { in tegra_pinctrl_clear_parked_bits()
690 unsigned int bank, reg; in tegra_pinctrl_clear_parked_bits() local
692 if (g->mux_reg != -1) { in tegra_pinctrl_clear_parked_bits()
693 bank = g->mux_bank; in tegra_pinctrl_clear_parked_bits()
694 reg = g->mux_reg; in tegra_pinctrl_clear_parked_bits()
696 bank = g->drv_bank; in tegra_pinctrl_clear_parked_bits()
697 reg = g->drv_reg; in tegra_pinctrl_clear_parked_bits()
700 val = pmx_readl(pmx, bank, reg); in tegra_pinctrl_clear_parked_bits()
701 val &= ~g->parked_bitmask; in tegra_pinctrl_clear_parked_bits()
702 pmx_writel(pmx, val, bank, reg); in tegra_pinctrl_clear_parked_bits()
721 u32 *backup_regs = pmx->backup_regs; in tegra_pinctrl_suspend()
726 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_suspend()
728 regs = pmx->regs[i]; in tegra_pinctrl_suspend()
733 return pinctrl_force_sleep(pmx->pctl); in tegra_pinctrl_suspend()
739 u32 *backup_regs = pmx->backup_regs; in tegra_pinctrl_resume()
744 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_resume()
746 regs = pmx->regs[i]; in tegra_pinctrl_resume()
752 readl_relaxed(pmx->regs[0]); in tegra_pinctrl_resume()
765 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); in tegra_pinctrl_gpio_node_has_range()
769 has_prop = of_find_property(np, "gpio-ranges", NULL); in tegra_pinctrl_gpio_node_has_range()
786 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in tegra_pinctrl_probe()
788 return -ENOMEM; in tegra_pinctrl_probe()
790 pmx->dev = &pdev->dev; in tegra_pinctrl_probe()
791 pmx->soc = soc_data; in tegra_pinctrl_probe()
795 * This over-allocates slightly, since not all groups are mux groups. in tegra_pinctrl_probe()
797 pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4, in tegra_pinctrl_probe()
798 sizeof(*pmx->group_pins), GFP_KERNEL); in tegra_pinctrl_probe()
799 if (!pmx->group_pins) in tegra_pinctrl_probe()
800 return -ENOMEM; in tegra_pinctrl_probe()
802 pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions, in tegra_pinctrl_probe()
803 sizeof(*pmx->functions), GFP_KERNEL); in tegra_pinctrl_probe()
804 if (!pmx->functions) in tegra_pinctrl_probe()
805 return -ENOMEM; in tegra_pinctrl_probe()
807 group_pins = pmx->group_pins; in tegra_pinctrl_probe()
809 for (fn = 0; fn < pmx->soc->nfunctions; fn++) { in tegra_pinctrl_probe()
810 struct tegra_function *func = &pmx->functions[fn]; in tegra_pinctrl_probe()
812 func->name = pmx->soc->functions[fn]; in tegra_pinctrl_probe()
813 func->groups = group_pins; in tegra_pinctrl_probe()
815 for (gn = 0; gn < pmx->soc->ngroups; gn++) { in tegra_pinctrl_probe()
816 const struct tegra_pingroup *g = &pmx->soc->groups[gn]; in tegra_pinctrl_probe()
818 if (g->mux_reg == -1) in tegra_pinctrl_probe()
822 if (g->funcs[gfn] == fn) in tegra_pinctrl_probe()
827 BUG_ON(group_pins - pmx->group_pins >= in tegra_pinctrl_probe()
828 pmx->soc->ngroups * 4); in tegra_pinctrl_probe()
829 *group_pins++ = g->name; in tegra_pinctrl_probe()
830 func->ngroups++; in tegra_pinctrl_probe()
834 pmx->gpio_range.name = "Tegra GPIOs"; in tegra_pinctrl_probe()
835 pmx->gpio_range.id = 0; in tegra_pinctrl_probe()
836 pmx->gpio_range.base = 0; in tegra_pinctrl_probe()
837 pmx->gpio_range.npins = pmx->soc->ngpios; in tegra_pinctrl_probe()
839 pmx->desc.pctlops = &tegra_pinctrl_ops; in tegra_pinctrl_probe()
840 pmx->desc.pmxops = &tegra_pinmux_ops; in tegra_pinctrl_probe()
841 pmx->desc.confops = &tegra_pinconf_ops; in tegra_pinctrl_probe()
842 pmx->desc.owner = THIS_MODULE; in tegra_pinctrl_probe()
843 pmx->desc.name = dev_name(&pdev->dev); in tegra_pinctrl_probe()
844 pmx->desc.pins = pmx->soc->pins; in tegra_pinctrl_probe()
845 pmx->desc.npins = pmx->soc->npins; in tegra_pinctrl_probe()
853 pmx->nbanks = i; in tegra_pinctrl_probe()
855 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), in tegra_pinctrl_probe()
857 if (!pmx->regs) in tegra_pinctrl_probe()
858 return -ENOMEM; in tegra_pinctrl_probe()
860 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, in tegra_pinctrl_probe()
862 if (!pmx->backup_regs) in tegra_pinctrl_probe()
863 return -ENOMEM; in tegra_pinctrl_probe()
865 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_probe()
866 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); in tegra_pinctrl_probe()
867 if (IS_ERR(pmx->regs[i])) in tegra_pinctrl_probe()
868 return PTR_ERR(pmx->regs[i]); in tegra_pinctrl_probe()
871 pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); in tegra_pinctrl_probe()
872 if (IS_ERR(pmx->pctl)) { in tegra_pinctrl_probe()
873 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in tegra_pinctrl_probe()
874 return PTR_ERR(pmx->pctl); in tegra_pinctrl_probe()
879 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) in tegra_pinctrl_probe()
880 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); in tegra_pinctrl_probe()
884 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); in tegra_pinctrl_probe()