Lines Matching full:bank
157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_bias() argument
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
199 stm32_gpio_backup_value(bank, offset, value); in __stm32_gpio_set()
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
225 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
227 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
232 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
234 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
240 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
242 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
250 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
253 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
263 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
268 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
283 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_init_valid_mask() local
284 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask()
291 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
293 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
298 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
321 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger() local
325 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
329 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
330 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
331 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
343 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type() local
362 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
369 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
370 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
373 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
377 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
389 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
391 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
429 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
430 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
442 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
454 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
457 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc()
485 bank); in stm32_gpio_domain_alloc()
493 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free() local
494 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free()
757 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
760 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
767 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
778 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
781 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
783 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
786 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
791 stm32_gpio_backup_mode(bank, pin, mode, alt); in stm32_pmx_set_mode()
794 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
799 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
807 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
809 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
813 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
817 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
828 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
842 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
848 return stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
855 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
858 return stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
892 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
895 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
900 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
911 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
914 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
919 stm32_gpio_backup_driving(bank, offset, drive); in stm32_pconf_set_driving()
922 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
927 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
933 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
935 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
938 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
943 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
946 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
951 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
962 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
965 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
970 stm32_gpio_backup_speed(bank, offset, speed); in stm32_pconf_set_speed()
973 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
978 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
984 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
989 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
994 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
997 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
1002 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1013 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1016 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1021 stm32_gpio_backup_bias(bank, offset, bias); in stm32_pconf_set_bias()
1024 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1029 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
1035 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1037 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1040 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1045 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
1051 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1054 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1057 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1060 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1071 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
1080 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1090 ret = stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
1093 ret = stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
1096 ret = stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
1099 ret = stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
1102 ret = stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
1105 ret = stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
1108 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
1189 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
1204 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1212 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
1213 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
1220 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
1228 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1229 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1230 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
1240 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1241 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1267 struct stm32_gpio_bank *bank, in stm32_pctrl_get_desc_pin_from_gpio() argument
1270 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; in stm32_pctrl_get_desc_pin_from_gpio()
1274 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ in stm32_pctrl_get_desc_pin_from_gpio()
1292 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
1294 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1303 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1304 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1309 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1310 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1311 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1313 err = clk_prepare_enable(bank->clk); in stm32_gpiolib_register_bank()
1319 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1321 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1325 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1333 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1334 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1339 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1344 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1347 bank->gpio_chip.base = -1; in stm32_gpiolib_register_bank()
1349 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1350 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1351 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1352 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1353 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1354 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1355 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1359 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1361 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1362 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1363 bank); in stm32_gpiolib_register_bank()
1365 if (!bank->domain) { in stm32_gpiolib_register_bank()
1378 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); in stm32_gpiolib_register_bank()
1385 bank->gpio_chip.names = (const char * const *)names; in stm32_gpiolib_register_bank()
1387 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1393 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1397 clk_disable_unprepare(bank->clk); in stm32_gpiolib_register_bank()
1613 dev_err(dev, "at least one GPIO bank is required\n"); in stm32_pctl_probe()
1623 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe() local
1626 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1627 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1632 bank->clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1633 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1635 return dev_err_probe(dev, PTR_ERR(bank->clk), in stm32_pctl_probe()
1666 struct stm32_gpio_bank *bank; in stm32_pinctrl_restore_gpio_regs() local
1682 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1684 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1686 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1689 ret = stm32_pmx_set_mode(bank, offset, mode, alt); in stm32_pinctrl_restore_gpio_regs()
1694 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1696 __stm32_gpio_set(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1699 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1701 ret = stm32_pconf_set_driving(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1705 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1707 ret = stm32_pconf_set_speed(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1711 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1713 ret = stm32_pconf_set_bias(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1718 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()