695 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynos_pinctrl_suspend_bank()  local
698 	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET  in exynos_pinctrl_suspend_bank()
700 	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_suspend_bank()
702 	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_suspend_bank()
704 	save->eint_mask = readl(regs + bank->irq_chip->eint_mask  in exynos_pinctrl_suspend_bank()
707 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);  in exynos_pinctrl_suspend_bank()
708 	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);  in exynos_pinctrl_suspend_bank()
709 	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);  in exynos_pinctrl_suspend_bank()
710 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);  in exynos_pinctrl_suspend_bank()
716 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynosauto_pinctrl_suspend_bank()  local
719 	save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);  in exynosauto_pinctrl_suspend_bank()
720 	save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);  in exynosauto_pinctrl_suspend_bank()
722 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);  in exynosauto_pinctrl_suspend_bank()
723 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);  in exynosauto_pinctrl_suspend_bank()
753 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynos_pinctrl_resume_bank()  local
758 			+ bank->eint_offset), save->eint_con);  in exynos_pinctrl_resume_bank()
761 			+ 2 * bank->eint_offset), save->eint_fltcon0);  in exynos_pinctrl_resume_bank()
764 			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);  in exynos_pinctrl_resume_bank()
767 			+ bank->eint_offset), save->eint_mask);  in exynos_pinctrl_resume_bank()
769 	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET  in exynos_pinctrl_resume_bank()
771 	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_resume_bank()
773 	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_resume_bank()
775 	writel(save->eint_mask, regs + bank->irq_chip->eint_mask  in exynos_pinctrl_resume_bank()
782 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynosauto_pinctrl_resume_bank()  local
786 		 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);  in exynosauto_pinctrl_resume_bank()
788 		 readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);  in exynosauto_pinctrl_resume_bank()
790 	writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);  in exynosauto_pinctrl_resume_bank()
791 	writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);  in exynosauto_pinctrl_resume_bank()