Lines Matching full:pctrl
142 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, in rzv2m_pinctrl_set_pfc_mode() argument
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
156 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
157 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
164 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_set_mux() local
181 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzv2m_pinctrl_set_mux()
184 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]), in rzv2m_pinctrl_set_mux()
219 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_dt_subnode_to_map() local
243 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzv2m_dt_subnode_to_map()
253 dev_err(pctrl->dev, in rzv2m_dt_subnode_to_map()
263 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzv2m_dt_subnode_to_map()
296 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
297 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzv2m_dt_subnode_to_map()
299 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
317 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzv2m_dt_subnode_to_map()
327 mutex_lock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
347 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
354 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzv2m_dt_subnode_to_map()
361 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
390 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_dt_node_to_map() local
418 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzv2m_dt_node_to_map()
427 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl, in rzv2m_validate_gpio_pin() argument
434 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzv2m_validate_gpio_pin()
437 data = pctrl->data->port_pin_configs[port]; in rzv2m_validate_gpio_pin()
444 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset, in rzv2m_rmw_pin_config() argument
447 void __iomem *addr = pctrl->base + offset; in rzv2m_rmw_pin_config()
451 spin_lock_irqsave(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
454 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
461 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_pinconf_get() local
463 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_get()
483 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) in rzv2m_pinctrl_pinconf_get()
499 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { in rzv2m_pinctrl_pinconf_get()
522 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; in rzv2m_pinctrl_pinconf_get()
548 arg = readl(pctrl->base + SR(port)) & BIT(bit); in rzv2m_pinctrl_pinconf_get()
565 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_pinconf_set() local
566 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_set()
587 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) in rzv2m_pinctrl_pinconf_set()
614 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val); in rzv2m_pinctrl_pinconf_set()
653 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index); in rzv2m_pinctrl_pinconf_set()
663 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); in rzv2m_pinctrl_pinconf_set()
752 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_request() local
761 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0); in rzv2m_gpio_request()
766 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port, in rzv2m_gpio_set_direction() argument
769 rzv2m_writel_we(pctrl->base + OE(port), bit, output); in rzv2m_gpio_set_direction()
770 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); in rzv2m_gpio_set_direction()
775 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_get_direction() local
779 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) in rzv2m_gpio_get_direction()
788 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_direction_input() local
792 rzv2m_gpio_set_direction(pctrl, port, bit, false); in rzv2m_gpio_direction_input()
800 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_set() local
804 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); in rzv2m_gpio_set()
810 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_direction_output() local
815 rzv2m_gpio_set_direction(pctrl, port, bit, true); in rzv2m_gpio_direction_output()
822 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_get() local
828 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); in rzv2m_gpio_get()
830 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); in rzv2m_gpio_get()
933 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl) in rzv2m_gpio_register() argument
935 struct device_node *np = pctrl->dev->of_node; in rzv2m_gpio_register()
936 struct gpio_chip *chip = &pctrl->gpio_chip; in rzv2m_gpio_register()
937 const char *name = dev_name(pctrl->dev); in rzv2m_gpio_register()
943 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzv2m_gpio_register()
948 of_args.args[2] != pctrl->data->n_port_pins) { in rzv2m_gpio_register()
949 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzv2m_gpio_register()
953 chip->names = pctrl->data->port_pins; in rzv2m_gpio_register()
962 chip->parent = pctrl->dev; in rzv2m_gpio_register()
967 pctrl->gpio_range.id = 0; in rzv2m_gpio_register()
968 pctrl->gpio_range.pin_base = 0; in rzv2m_gpio_register()
969 pctrl->gpio_range.base = 0; in rzv2m_gpio_register()
970 pctrl->gpio_range.npins = chip->ngpio; in rzv2m_gpio_register()
971 pctrl->gpio_range.name = chip->label; in rzv2m_gpio_register()
972 pctrl->gpio_range.gc = chip; in rzv2m_gpio_register()
973 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzv2m_gpio_register()
975 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzv2m_gpio_register()
979 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzv2m_gpio_register()
984 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) in rzv2m_pinctrl_register() argument
991 pctrl->desc.name = DRV_NAME; in rzv2m_pinctrl_register()
992 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzv2m_pinctrl_register()
993 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; in rzv2m_pinctrl_register()
994 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; in rzv2m_pinctrl_register()
995 pctrl->desc.confops = &rzv2m_pinctrl_confops; in rzv2m_pinctrl_register()
996 pctrl->desc.owner = THIS_MODULE; in rzv2m_pinctrl_register()
998 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzv2m_pinctrl_register()
1002 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzv2m_pinctrl_register()
1007 pctrl->pins = pins; in rzv2m_pinctrl_register()
1008 pctrl->desc.pins = pins; in rzv2m_pinctrl_register()
1010 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzv2m_pinctrl_register()
1012 pins[i].name = pctrl->data->port_pins[i]; in rzv2m_pinctrl_register()
1015 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzv2m_pinctrl_register()
1019 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzv2m_pinctrl_register()
1020 unsigned int index = pctrl->data->n_port_pins + i; in rzv2m_pinctrl_register()
1023 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzv2m_pinctrl_register()
1024 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzv2m_pinctrl_register()
1028 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzv2m_pinctrl_register()
1029 &pctrl->pctl); in rzv2m_pinctrl_register()
1031 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzv2m_pinctrl_register()
1035 ret = pinctrl_enable(pctrl->pctl); in rzv2m_pinctrl_register()
1037 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzv2m_pinctrl_register()
1041 ret = rzv2m_gpio_register(pctrl); in rzv2m_pinctrl_register()
1043 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzv2m_pinctrl_register()
1052 struct rzv2m_pinctrl *pctrl; in rzv2m_pinctrl_probe() local
1056 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzv2m_pinctrl_probe()
1057 if (!pctrl) in rzv2m_pinctrl_probe()
1060 pctrl->dev = &pdev->dev; in rzv2m_pinctrl_probe()
1062 pctrl->data = of_device_get_match_data(&pdev->dev); in rzv2m_pinctrl_probe()
1063 if (!pctrl->data) in rzv2m_pinctrl_probe()
1066 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzv2m_pinctrl_probe()
1067 if (IS_ERR(pctrl->base)) in rzv2m_pinctrl_probe()
1068 return PTR_ERR(pctrl->base); in rzv2m_pinctrl_probe()
1070 clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzv2m_pinctrl_probe()
1072 return dev_err_probe(pctrl->dev, PTR_ERR(clk), in rzv2m_pinctrl_probe()
1075 spin_lock_init(&pctrl->lock); in rzv2m_pinctrl_probe()
1076 mutex_init(&pctrl->mutex); in rzv2m_pinctrl_probe()
1078 platform_set_drvdata(pdev, pctrl); in rzv2m_pinctrl_probe()
1080 ret = rzv2m_pinctrl_register(pctrl); in rzv2m_pinctrl_probe()
1084 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzv2m_pinctrl_probe()