238 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,  in rzg2l_pinctrl_set_pfc_mode()  argument
241 	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;  in rzg2l_pinctrl_set_pfc_mode()
245 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_pinctrl_set_pfc_mode()
248 	reg = readw(pctrl->base + PM(off));  in rzg2l_pinctrl_set_pfc_mode()
250 	writew(reg, pctrl->base + PM(off));  in rzg2l_pinctrl_set_pfc_mode()
253 	reg = readb(pctrl->base + PMC(off));  in rzg2l_pinctrl_set_pfc_mode()
254 	writeb(reg & ~BIT(pin), pctrl->base + PMC(off));  in rzg2l_pinctrl_set_pfc_mode()
257 	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
258 	writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* B0WI=0, PFCWE=1 */  in rzg2l_pinctrl_set_pfc_mode()
261 	reg = readl(pctrl->base + PFC(off));  in rzg2l_pinctrl_set_pfc_mode()
263 	writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));  in rzg2l_pinctrl_set_pfc_mode()
266 	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
267 	writel(PWPR_B0WI, pctrl->base + regs->pwpr);	/* B0WI=1, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
270 	reg = readb(pctrl->base + PMC(off));  in rzg2l_pinctrl_set_pfc_mode()
271 	writeb(reg | BIT(pin), pctrl->base + PMC(off));  in rzg2l_pinctrl_set_pfc_mode()
273 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_pinctrl_set_pfc_mode()
280 	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in rzg2l_pinctrl_set_mux()  local
281 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_pinctrl_set_mux()
298 		unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;  in rzg2l_pinctrl_set_mux()
302 		dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",  in rzg2l_pinctrl_set_mux()
305 		rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);  in rzg2l_pinctrl_set_mux()
339 	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in rzg2l_dt_subnode_to_map()  local
363 		dev_err(pctrl->dev, "Invalid pins list in DT\n");  in rzg2l_dt_subnode_to_map()
373 		dev_err(pctrl->dev,  in rzg2l_dt_subnode_to_map()
383 		dev_err(pctrl->dev, "DT node must contain a config\n");  in rzg2l_dt_subnode_to_map()
419 	pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);  in rzg2l_dt_subnode_to_map()
420 	psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),  in rzg2l_dt_subnode_to_map()
422 	pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);  in rzg2l_dt_subnode_to_map()
440 		name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",  in rzg2l_dt_subnode_to_map()
450 	mutex_lock(&pctrl->mutex);  in rzg2l_dt_subnode_to_map()
470 	mutex_unlock(&pctrl->mutex);  in rzg2l_dt_subnode_to_map()
487 	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);  in rzg2l_dt_subnode_to_map()
494 	mutex_unlock(&pctrl->mutex);  in rzg2l_dt_subnode_to_map()
523 	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in rzg2l_dt_node_to_map()  local
551 	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);  in rzg2l_dt_node_to_map()
560 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,  in rzg2l_validate_gpio_pin()  argument
567 	if (bit >= pincount || port >= pctrl->data->n_port_pins)  in rzg2l_validate_gpio_pin()
570 	data = pctrl->data->port_pin_configs[port];  in rzg2l_validate_gpio_pin()
577 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,  in rzg2l_read_pin_config()  argument
580 	void __iomem *addr = pctrl->base + offset;  in rzg2l_read_pin_config()
591 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,  in rzg2l_rmw_pin_config()  argument
594 	void __iomem *addr = pctrl->base + offset;  in rzg2l_rmw_pin_config()
604 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_rmw_pin_config()
607 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_rmw_pin_config()
626 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)  in rzg2l_get_power_source()  argument
628 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_get_power_source()
634 		return pctrl->settings[pin].power_source;  in rzg2l_get_power_source()
640 	val = readb(pctrl->base + pwr_reg);  in rzg2l_get_power_source()
654 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)  in rzg2l_set_power_source()  argument
656 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_set_power_source()
662 		pctrl->settings[pin].power_source = ps;  in rzg2l_set_power_source()
684 	writeb(val, pctrl->base + pwr_reg);  in rzg2l_set_power_source()
685 	pctrl->settings[pin].power_source = ps;  in rzg2l_set_power_source()
759 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,  in rzg2l_ds_is_supported()  argument
763 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_ds_is_supported()
813 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)  in rzg2l_read_oen()  argument
815 	u8 max_port = pctrl->data->hwcfg->oen_max_port;  in rzg2l_read_oen()
816 	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;  in rzg2l_read_oen()
824 	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));  in rzg2l_read_oen()
827 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)  in rzg2l_write_oen()  argument
829 	u8 max_port = pctrl->data->hwcfg->oen_max_port;  in rzg2l_write_oen()
830 	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;  in rzg2l_write_oen()
839 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_write_oen()
840 	val = readb(pctrl->base + ETH_MODE);  in rzg2l_write_oen()
845 	writeb(val, pctrl->base + ETH_MODE);  in rzg2l_write_oen()
846 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_write_oen()
855 	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in rzg2l_pinctrl_pinconf_get()  local
857 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_pinctrl_pinconf_get()
858 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];  in rzg2l_pinctrl_pinconf_get()
875 		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))  in rzg2l_pinctrl_pinconf_get()
883 		arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);  in rzg2l_pinctrl_pinconf_get()
889 		arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);  in rzg2l_pinctrl_pinconf_get()
895 		ret = rzg2l_get_power_source(pctrl, _pin, cfg);  in rzg2l_pinctrl_pinconf_get()
907 		index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);  in rzg2l_pinctrl_pinconf_get()
924 		ret = rzg2l_get_power_source(pctrl, _pin, cfg);  in rzg2l_pinctrl_pinconf_get()
928 		val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);  in rzg2l_pinctrl_pinconf_get()
939 		index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);  in rzg2l_pinctrl_pinconf_get()
958 	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in rzg2l_pinctrl_pinconf_set()  local
959 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];  in rzg2l_pinctrl_pinconf_set()
960 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_pinctrl_pinconf_set()
961 	struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];  in rzg2l_pinctrl_pinconf_set()
979 		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))  in rzg2l_pinctrl_pinconf_set()
992 			rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);  in rzg2l_pinctrl_pinconf_set()
997 			ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);  in rzg2l_pinctrl_pinconf_set()
1020 			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);  in rzg2l_pinctrl_pinconf_set()
1044 			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);  in rzg2l_pinctrl_pinconf_set()
1053 	if (settings.power_source != pctrl->settings[_pin].power_source) {  in rzg2l_pinctrl_pinconf_set()
1059 		ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);  in rzg2l_pinctrl_pinconf_set()
1065 	if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {  in rzg2l_pinctrl_pinconf_set()
1070 		ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,  in rzg2l_pinctrl_pinconf_set()
1081 		rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);  in rzg2l_pinctrl_pinconf_set()
1082 		pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;  in rzg2l_pinctrl_pinconf_set()
1165 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_request()  local
1166 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];  in rzg2l_gpio_request()
1175 	ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);  in rzg2l_gpio_request()
1183 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_request()
1186 	reg8 = readb(pctrl->base + PMC(off));  in rzg2l_gpio_request()
1188 	writeb(reg8, pctrl->base + PMC(off));  in rzg2l_gpio_request()
1190 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_request()
1195 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,  in rzg2l_gpio_set_direction()  argument
1198 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];  in rzg2l_gpio_set_direction()
1205 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_set_direction()
1207 	reg16 = readw(pctrl->base + PM(off));  in rzg2l_gpio_set_direction()
1211 	writew(reg16, pctrl->base + PM(off));  in rzg2l_gpio_set_direction()
1213 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_set_direction()
1218 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_get_direction()  local
1219 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];  in rzg2l_gpio_get_direction()
1224 	if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {  in rzg2l_gpio_get_direction()
1227 		reg16 = readw(pctrl->base + PM(off));  in rzg2l_gpio_get_direction()
1239 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_direction_input()  local
1241 	rzg2l_gpio_set_direction(pctrl, offset, false);  in rzg2l_gpio_direction_input()
1249 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_set()  local
1250 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];  in rzg2l_gpio_set()
1257 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_set()
1259 	reg8 = readb(pctrl->base + P(off));  in rzg2l_gpio_set()
1262 		writeb(reg8 | BIT(bit), pctrl->base + P(off));  in rzg2l_gpio_set()
1264 		writeb(reg8 & ~BIT(bit), pctrl->base + P(off));  in rzg2l_gpio_set()
1266 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_set()
1272 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_direction_output()  local
1275 	rzg2l_gpio_set_direction(pctrl, offset, true);  in rzg2l_gpio_direction_output()
1282 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);  in rzg2l_gpio_get()  local
1283 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];  in rzg2l_gpio_get()
1289 	reg16 = readw(pctrl->base + PM(off));  in rzg2l_gpio_get()
1293 		return !!(readb(pctrl->base + PIN(off)) & BIT(bit));  in rzg2l_gpio_get()
1295 		return !!(readb(pctrl->base + P(off)) & BIT(bit));  in rzg2l_gpio_get()
1624 	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);  in rzg2l_gpio_irq_disable()  local
1626 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];  in rzg2l_gpio_irq_disable()
1635 	addr = pctrl->base + ISEL(off);  in rzg2l_gpio_irq_disable()
1641 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_irq_disable()
1643 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_irq_disable()
1651 	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);  in rzg2l_gpio_irq_enable()  local
1653 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];  in rzg2l_gpio_irq_enable()
1662 	addr = pctrl->base + ISEL(off);  in rzg2l_gpio_irq_enable()
1668 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_irq_enable()
1670 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_irq_enable()
1712 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);  in rzg2l_gpio_child_to_parent_hwirq()  local
1716 	gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);  in rzg2l_gpio_child_to_parent_hwirq()
1720 	spin_lock_irqsave(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_child_to_parent_hwirq()
1721 	irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));  in rzg2l_gpio_child_to_parent_hwirq()
1722 	spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_child_to_parent_hwirq()
1725 	pctrl->hwirq[irq] = child;  in rzg2l_gpio_child_to_parent_hwirq()
1757 		struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);  in rzg2l_gpio_irq_domain_free()  local
1763 			if (pctrl->hwirq[i] == hwirq) {  in rzg2l_gpio_irq_domain_free()
1764 				spin_lock_irqsave(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_irq_domain_free()
1765 				bitmap_release_region(pctrl->tint_slot, i, get_order(1));  in rzg2l_gpio_irq_domain_free()
1766 				spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_irq_domain_free()
1767 				pctrl->hwirq[i] = 0;  in rzg2l_gpio_irq_domain_free()
1779 	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);  in rzg2l_init_irq_valid_mask()  local
1780 	struct gpio_chip *chip = &pctrl->gpio_chip;  in rzg2l_init_irq_valid_mask()
1790 		if (port >= pctrl->data->n_ports ||  in rzg2l_init_irq_valid_mask()
1791 		    bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))  in rzg2l_init_irq_valid_mask()
1796 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)  in rzg2l_gpio_register()  argument
1798 	struct device_node *np = pctrl->dev->of_node;  in rzg2l_gpio_register()
1799 	struct gpio_chip *chip = &pctrl->gpio_chip;  in rzg2l_gpio_register()
1800 	const char *name = dev_name(pctrl->dev);  in rzg2l_gpio_register()
1818 		dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");  in rzg2l_gpio_register()
1823 	    of_args.args[2] != pctrl->data->n_port_pins) {  in rzg2l_gpio_register()
1824 		dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");  in rzg2l_gpio_register()
1828 	chip->names = pctrl->data->port_pins;  in rzg2l_gpio_register()
1837 	chip->parent = pctrl->dev;  in rzg2l_gpio_register()
1851 	pctrl->gpio_range.id = 0;  in rzg2l_gpio_register()
1852 	pctrl->gpio_range.pin_base = 0;  in rzg2l_gpio_register()
1853 	pctrl->gpio_range.base = 0;  in rzg2l_gpio_register()
1854 	pctrl->gpio_range.npins = chip->ngpio;  in rzg2l_gpio_register()
1855 	pctrl->gpio_range.name = chip->label;  in rzg2l_gpio_register()
1856 	pctrl->gpio_range.gc = chip;  in rzg2l_gpio_register()
1857 	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);  in rzg2l_gpio_register()
1859 		dev_err(pctrl->dev, "failed to add GPIO controller\n");  in rzg2l_gpio_register()
1863 	dev_dbg(pctrl->dev, "Registered gpio controller\n");  in rzg2l_gpio_register()
1868 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)  in rzg2l_pinctrl_register()  argument
1870 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;  in rzg2l_pinctrl_register()
1876 	pctrl->desc.name = DRV_NAME;  in rzg2l_pinctrl_register()
1877 	pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;  in rzg2l_pinctrl_register()
1878 	pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;  in rzg2l_pinctrl_register()
1879 	pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;  in rzg2l_pinctrl_register()
1880 	pctrl->desc.confops = &rzg2l_pinctrl_confops;  in rzg2l_pinctrl_register()
1881 	pctrl->desc.owner = THIS_MODULE;  in rzg2l_pinctrl_register()
1883 	pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);  in rzg2l_pinctrl_register()
1887 	pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,  in rzg2l_pinctrl_register()
1892 	pctrl->pins = pins;  in rzg2l_pinctrl_register()
1893 	pctrl->desc.pins = pins;  in rzg2l_pinctrl_register()
1895 	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {  in rzg2l_pinctrl_register()
1897 		pins[i].name = pctrl->data->port_pins[i];  in rzg2l_pinctrl_register()
1900 		pin_data[i] = pctrl->data->port_pin_configs[j];  in rzg2l_pinctrl_register()
1904 	for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {  in rzg2l_pinctrl_register()
1905 		unsigned int index = pctrl->data->n_port_pins + i;  in rzg2l_pinctrl_register()
1908 		pins[index].name = pctrl->data->dedicated_pins[i].name;  in rzg2l_pinctrl_register()
1909 		pin_data[index] = pctrl->data->dedicated_pins[i].config;  in rzg2l_pinctrl_register()
1913 	pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),  in rzg2l_pinctrl_register()
1915 	if (!pctrl->settings)  in rzg2l_pinctrl_register()
1918 	for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {  in rzg2l_pinctrl_register()
1920 			pctrl->settings[i].power_source = 3300;  in rzg2l_pinctrl_register()
1922 			ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);  in rzg2l_pinctrl_register()
1925 			pctrl->settings[i].power_source = ret;  in rzg2l_pinctrl_register()
1929 	ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,  in rzg2l_pinctrl_register()
1930 					     &pctrl->pctl);  in rzg2l_pinctrl_register()
1932 		dev_err(pctrl->dev, "pinctrl registration failed\n");  in rzg2l_pinctrl_register()
1936 	ret = pinctrl_enable(pctrl->pctl);  in rzg2l_pinctrl_register()
1938 		dev_err(pctrl->dev, "pinctrl enable failed\n");  in rzg2l_pinctrl_register()
1942 	ret = rzg2l_gpio_register(pctrl);  in rzg2l_pinctrl_register()
1944 		dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);  in rzg2l_pinctrl_register()
1953 	struct rzg2l_pinctrl *pctrl;  in rzg2l_pinctrl_probe()  local
1966 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in rzg2l_pinctrl_probe()
1967 	if (!pctrl)  in rzg2l_pinctrl_probe()
1970 	pctrl->dev = &pdev->dev;  in rzg2l_pinctrl_probe()
1972 	pctrl->data = of_device_get_match_data(&pdev->dev);  in rzg2l_pinctrl_probe()
1973 	if (!pctrl->data)  in rzg2l_pinctrl_probe()
1976 	pctrl->base = devm_platform_ioremap_resource(pdev, 0);  in rzg2l_pinctrl_probe()
1977 	if (IS_ERR(pctrl->base))  in rzg2l_pinctrl_probe()
1978 		return PTR_ERR(pctrl->base);  in rzg2l_pinctrl_probe()
1980 	clk = devm_clk_get_enabled(pctrl->dev, NULL);  in rzg2l_pinctrl_probe()
1982 		return dev_err_probe(pctrl->dev, PTR_ERR(clk),  in rzg2l_pinctrl_probe()
1985 	spin_lock_init(&pctrl->lock);  in rzg2l_pinctrl_probe()
1986 	spin_lock_init(&pctrl->bitmap_lock);  in rzg2l_pinctrl_probe()
1987 	mutex_init(&pctrl->mutex);  in rzg2l_pinctrl_probe()
1989 	platform_set_drvdata(pdev, pctrl);  in rzg2l_pinctrl_probe()
1991 	ret = rzg2l_pinctrl_register(pctrl);  in rzg2l_pinctrl_probe()
1995 	dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);  in rzg2l_pinctrl_probe()