Lines Matching +full:stih407 +full:- +full:irq +full:- +full:syscfg
1 // SPDX-License-Identifier: GPL-2.0-only
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
114 * +----------------+ |
115 *[22] | retime-invclk | |
116 * +----------------+ v
117 *[21] |retime-clknotdat| [Retime-type ]
118 * +----------------+ ^
119 *[20] | retime-de | |
120 * +----------------+-------------
121 *[19:18]| retime-clk |------>[Retime-Clk ]
122 * +----------------+
123 *[17:16]| reserved-1 |
124 * +----------------+
125 *[15..0]| retime-delay |------>[Retime Delay]
126 * +----------------+
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
282 * --------------------------------------------------------
283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
284 * --------------------------------------------------------
288 * ------- ----------------------------
289 * [0-3] - Description
290 * ------- ----------------------------
291 * 0000 - No edge IRQ.
292 * 0001 - Falling edge IRQ.
293 * 0010 - Rising edge IRQ.
294 * 0011 - Rising and Falling edge IRQ.
295 * ------- ----------------------------
360 .oe = -1, /* Not Available */
361 .pu = -1, /* Not Available */
373 return &bank->pc; in st_get_pio_control()
390 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
391 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
392 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
424 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
440 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
456 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
460 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
461 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
463 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
464 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
468 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
492 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
493 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
495 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
496 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
523 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
524 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
527 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
530 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
533 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
536 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
539 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
545 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
547 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
562 info->data, config); in st_pinconf_set_retime_dedicated()
563 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
574 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
582 if (pc->oe) { in st_pinconf_get_direction()
583 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
588 if (pc->pu) { in st_pinconf_get_direction()
589 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
594 if (pc->od) { in st_pinconf_get_direction()
595 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
604 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
605 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
609 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
612 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
615 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
618 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
621 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
624 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
625 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
640 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
642 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
648 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
691 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
734 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
753 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
756 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
771 return info->ngroups; in st_pctl_get_groups_count()
779 return info->groups[selector].name; in st_pctl_get_group_name()
787 if (selector >= info->ngroups) in st_pctl_get_group_pins()
788 return -EINVAL; in st_pctl_get_group_pins()
790 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
791 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
801 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
802 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
803 return &info->groups[i]; in st_pctl_find_group_by_name()
814 struct device *dev = info->dev; in st_pctl_dt_node_to_map()
819 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
822 return -EINVAL; in st_pctl_dt_node_to_map()
825 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
828 return -ENOMEM; in st_pctl_dt_node_to_map()
833 return -EINVAL; in st_pctl_dt_node_to_map()
839 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
840 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
845 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
848 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
849 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
853 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
876 return info->nfunctions; in st_pmx_get_funcs_count()
884 return info->functions[selector].name; in st_pmx_get_fname()
891 *grps = info->functions[selector].groups; in st_pmx_get_groups()
892 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
901 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
905 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
923 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
943 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
945 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
946 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
954 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
956 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
957 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
1002 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1005 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1013 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); in st_pinconf_dbg_show()
1016 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1040 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1041 info->nbanks++; in st_pctl_dt_child_count()
1043 info->nfunctions++; in st_pctl_dt_child_count()
1044 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1052 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1053 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1054 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1056 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1057 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1068 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1069 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1070 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1071 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1072 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1073 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1074 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1076 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1077 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1078 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1079 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1080 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1088 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1089 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1090 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1092 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1093 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1095 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1100 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1101 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1102 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1112 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1113 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1115 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1118 return -EINVAL; in st_pctl_dt_setup_retime()
1137 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1144 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1145 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1146 struct device *dev = info->dev; in st_parse_syscfgs()
1147 struct regmap *regmap = info->regmap; in st_parse_syscfgs()
1149 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1150 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1151 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1152 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1155 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1156 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1167 int retval = -EINVAL; in st_pctl_dt_calculate_pin()
1172 return -EINVAL; in st_pctl_dt_calculate_pin()
1174 for (i = 0; i < info->nbanks; i++) { in st_pctl_dt_calculate_pin()
1175 chip = &info->banks[i].gpio_chip; in st_pctl_dt_calculate_pin()
1176 if (chip->fwnode == of_fwnode_handle(np)) { in st_pctl_dt_calculate_pin()
1177 if (offset < chip->ngpio) in st_pctl_dt_calculate_pin()
1178 retval = chip->base + offset; in st_pctl_dt_calculate_pin()
1197 struct device *dev = info->dev; in st_pctl_dt_parse_groups()
1206 return -ENODATA; in st_pctl_dt_parse_groups()
1210 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1213 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1217 ret = -EINVAL; in st_pctl_dt_parse_groups()
1222 grp->npins = npins; in st_pctl_dt_parse_groups()
1223 grp->name = np->name; in st_pctl_dt_parse_groups()
1224 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); in st_pctl_dt_parse_groups()
1225 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); in st_pctl_dt_parse_groups()
1227 if (!grp->pins || !grp->pin_conf) { in st_pctl_dt_parse_groups()
1228 ret = -ENOMEM; in st_pctl_dt_parse_groups()
1234 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1236 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1237 list = pp->value; in st_pctl_dt_parse_groups()
1238 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1243 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); in st_pctl_dt_parse_groups()
1244 conf->name = pp->name; in st_pctl_dt_parse_groups()
1245 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1247 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1248 conf->config = 0; in st_pctl_dt_parse_groups()
1250 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1254 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1256 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1259 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1273 struct device *dev = info->dev; in st_pctl_parse_functions()
1279 func = &info->functions[index]; in st_pctl_parse_functions()
1280 func->name = np->name; in st_pctl_parse_functions()
1281 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1282 if (func->ngroups == 0) in st_pctl_parse_functions()
1283 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); in st_pctl_parse_functions()
1284 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in st_pctl_parse_functions()
1285 if (!func->groups) in st_pctl_parse_functions()
1286 return -ENOMEM; in st_pctl_parse_functions()
1290 func->groups[i] = child->name; in st_pctl_parse_functions()
1291 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1299 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); in st_pctl_parse_functions()
1309 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1319 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1326 pinctrl_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1328 return gpiochip_reqres_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1335 gpiochip_relres_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1343 int comp, pin = d->hwirq; in st_gpio_irq_set_type()
1363 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1367 return -EINVAL; in st_gpio_irq_set_type()
1370 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1371 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1373 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1374 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1376 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1379 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1396 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1400 * step-1 ________ __________
1401 * | | step - 3
1403 * step -2 |_____|
1414 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1415 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1416 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1419 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1420 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1421 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1434 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1437 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1438 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1445 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); in __gpio_irq_handler()
1471 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1473 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1474 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1504 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank()
1505 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1506 struct device *dev = info->dev; in st_gpiolib_register_bank()
1512 return -ENODEV; in st_gpiolib_register_bank()
1514 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1515 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1516 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1518 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1519 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1520 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1521 bank->gpio_chip.fwnode = of_fwnode_handle(np); in st_gpiolib_register_bank()
1522 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1523 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1525 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1526 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1528 range->id = bank_num; in st_gpiolib_register_bank()
1529 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1530 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1531 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1535 * interrupt-wirings. in st_gpiolib_register_bank()
1541 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1542 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1543 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1544 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1545 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1549 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1556 /* This is not a valid IRQ */ in st_gpiolib_register_bank()
1558 dev_err(dev, "invalid IRQ for %pOF bank\n", np); in st_gpiolib_register_bank()
1562 if (!info->irqmux_base) { in st_gpiolib_register_bank()
1567 girq = &bank->gpio_chip.irq; in st_gpiolib_register_bank()
1569 girq->parent_handler = st_gpio_irq_handler; in st_gpiolib_register_bank()
1570 girq->num_parents = 1; in st_gpiolib_register_bank()
1571 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in st_gpiolib_register_bank()
1573 if (!girq->parents) in st_gpiolib_register_bank()
1574 return -ENOMEM; in st_gpiolib_register_bank()
1575 girq->parents[0] = gpio_irq; in st_gpiolib_register_bank()
1576 girq->default_type = IRQ_TYPE_NONE; in st_gpiolib_register_bank()
1577 girq->handler = handle_simple_irq; in st_gpiolib_register_bank()
1581 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1584 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1590 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1591 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1592 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1593 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1600 struct device *dev = &pdev->dev; in st_pctl_probe_dt()
1604 struct device_node *np = dev->of_node; in st_pctl_probe_dt()
1607 int irq = 0; in st_pctl_probe_dt() local
1610 if (!info->nbanks) in st_pctl_probe_dt()
1611 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); in st_pctl_probe_dt()
1613 dev_info(dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1614 dev_info(dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1615 dev_info(dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1617 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1619 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in st_pctl_probe_dt()
1621 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1623 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1624 return -ENOMEM; in st_pctl_probe_dt()
1626 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1627 if (IS_ERR(info->regmap)) in st_pctl_probe_dt()
1628 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1629 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1631 irq = platform_get_irq(pdev, 0); in st_pctl_probe_dt()
1633 if (irq > 0) { in st_pctl_probe_dt()
1634 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); in st_pctl_probe_dt()
1635 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1636 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1638 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, in st_pctl_probe_dt()
1642 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1643 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1645 return -ENOMEM; in st_pctl_probe_dt()
1647 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1651 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1661 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1662 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1671 pdesc->number = k; in st_pctl_probe_dt()
1672 pdesc->name = pin_names[j]; in st_pctl_probe_dt()
1693 struct device *dev = &pdev->dev; in st_pctl_probe()
1698 if (!dev->of_node) { in st_pctl_probe()
1700 return -EINVAL; in st_pctl_probe()
1705 return -ENOMEM; in st_pctl_probe()
1709 return -ENOMEM; in st_pctl_probe()
1711 info->dev = dev; in st_pctl_probe()
1717 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1718 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1719 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1720 pctl_desc->confops = &st_confops; in st_pctl_probe()
1721 pctl_desc->name = dev_name(dev); in st_pctl_probe()
1723 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); in st_pctl_probe()
1724 if (IS_ERR(info->pctl)) in st_pctl_probe()
1725 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); in st_pctl_probe()
1727 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1728 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1735 .name = "st-pinctrl",