Lines Matching +full:mux +full:- +full:add +full:- +full:data
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
102 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @npins: number pins with the same mux value of gpio function
105 * @gpiofunc: mux value of gpio function
116 * struct pcs_data - wrapper for data needed by pinctrl framework
130 * struct pcs_soc_data - SoC specific settings
135 * @rearm: optional SoC specific wake-up rearm function
146 * struct pcs_device - pinctrl device instance
156 * @socdata: soc specific data
159 * @width: bits per mux register
162 * @foff: value to turn mux off
164 * @bits_per_mux: number of bits per mux
209 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
210 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
211 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
235 * generic. But at least on omaps, some mux registers are performance
275 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
277 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
280 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
290 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
305 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
307 if (pcs->bits_per_mux) in pcs_pin_dbg_show()
308 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); in pcs_pin_dbg_show()
310 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
321 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
347 setting = pdesc->mux_setting; in pcs_get_function()
349 return -ENOTSUPP; in pcs_get_function()
350 fselector = setting->func; in pcs_get_function()
352 *func = function->data; in pcs_get_function()
354 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
356 return -ENOTSUPP; in pcs_get_function()
371 if (!pcs->fmask) in pcs_set_mux()
375 return -EINVAL; in pcs_set_mux()
376 func = function->data; in pcs_set_mux()
378 return -EINVAL; in pcs_set_mux()
380 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
381 func->name, fselector); in pcs_set_mux()
383 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
388 vals = &func->vals[i]; in pcs_set_mux()
389 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
390 val = pcs->read(vals->reg); in pcs_set_mux()
392 if (pcs->bits_per_mux) in pcs_set_mux()
393 mask = vals->mask; in pcs_set_mux()
395 mask = pcs->fmask; in pcs_set_mux()
398 val |= (vals->val & mask); in pcs_set_mux()
399 pcs->write(val, vals->reg); in pcs_set_mux()
400 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
412 unsigned data; in pcs_request_gpio() local
415 if (!pcs->fmask) in pcs_request_gpio()
416 return -ENOTSUPP; in pcs_request_gpio()
418 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
422 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
423 || pin < frange->offset) in pcs_request_gpio()
428 if (pcs->bits_per_mux) { in pcs_request_gpio()
431 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
432 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
433 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
434 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
436 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
437 data &= ~pcs->fmask; in pcs_request_gpio()
438 data |= frange->gpiofunc; in pcs_request_gpio()
439 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
490 unsigned offset = 0, data = 0, i, j, ret; in pcs_pinconf_get() local
496 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
503 return -ENOTSUPP; in pcs_pinconf_get()
505 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
509 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
510 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
511 switch (func->conf[i].param) { in pcs_pinconf_get()
516 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
517 (data == func->conf[i].disable)) in pcs_pinconf_get()
518 return -ENOTSUPP; in pcs_pinconf_get()
523 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
524 switch (func->conf[j].param) { in pcs_pinconf_get()
526 if (data != func->conf[j].enable) in pcs_pinconf_get()
527 return -ENOTSUPP; in pcs_pinconf_get()
533 *config = data; in pcs_pinconf_get()
540 *config = data; in pcs_pinconf_get()
545 return -ENOTSUPP; in pcs_pinconf_get()
554 unsigned offset = 0, shift = 0, i, data, ret; in pcs_pinconf_set() local
563 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
565 != func->conf[i].param) in pcs_pinconf_set()
568 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
569 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
571 switch (func->conf[i].param) { in pcs_pinconf_set()
578 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
579 data &= ~func->conf[i].mask; in pcs_pinconf_set()
580 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
592 data &= ~func->conf[i].mask; in pcs_pinconf_set()
594 data |= func->conf[i].enable; in pcs_pinconf_set()
596 data |= func->conf[i].disable; in pcs_pinconf_set()
599 return -ENOTSUPP; in pcs_pinconf_set()
601 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
605 if (i >= func->nconfs) in pcs_pinconf_set()
606 return -ENOTSUPP; in pcs_pinconf_set()
624 return -ENOTSUPP; in pcs_pinconf_group_get()
627 return -ENOTSUPP; in pcs_pinconf_group_get()
646 return -ENOTSUPP; in pcs_pinconf_group_set()
680 * pcs_add_pin() - add a pin to the static per controller pin array
686 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
690 i = pcs->pins.cur; in pcs_add_pin()
691 if (i >= pcs->desc.npins) { in pcs_add_pin()
692 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
693 pcs->desc.npins); in pcs_add_pin()
694 return -ENOMEM; in pcs_add_pin()
697 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
700 val = pcs->read(pcs->base + offset); in pcs_add_pin()
701 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
702 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
703 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
704 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
705 pcs->write(val, pcs->base + offset); in pcs_add_pin()
709 pin = &pcs->pins.pa[i]; in pcs_add_pin()
710 pin->number = i; in pcs_add_pin()
711 pcs->pins.cur++; in pcs_add_pin()
717 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
729 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
731 if (pcs->bits_per_mux && pcs->fmask) { in pcs_allocate_pin_table()
732 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
733 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
735 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
738 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
739 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
740 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
742 if (!pcs->pins.pa) in pcs_allocate_pin_table()
743 return -ENOMEM; in pcs_allocate_pin_table()
745 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
746 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
748 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
755 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
764 * pcs_add_function() - adds a new function to the function list
768 * @vals: array of mux register value pairs used by the function
769 * @nvals: number of mux register value pairs
786 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
788 return -ENOMEM; in pcs_add_function()
790 function->vals = vals; in pcs_add_function()
791 function->nvals = nvals; in pcs_add_function()
792 function->name = name; in pcs_add_function()
794 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
798 devm_kfree(pcs->dev, function); in pcs_add_function()
808 * pcs_get_pin_by_offset() - get a pin index based on the register offset
818 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
819 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
820 offset, pcs->size); in pcs_get_pin_by_offset()
821 return -EINVAL; in pcs_get_pin_by_offset()
824 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
825 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
827 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
833 * check whether data matches enable bits or disable bits
837 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) in pcs_config_match() argument
839 int ret = -EINVAL; in pcs_config_match()
841 if (data == enable) in pcs_config_match()
843 else if (data == disable) in pcs_config_match()
852 (*conf)->param = param; in add_config()
853 (*conf)->val = value; in add_config()
854 (*conf)->enable = enable; in add_config()
855 (*conf)->disable = disable; in add_config()
856 (*conf)->mask = mask; in add_config()
867 /* add pinconf setting with 2 parameters */
880 shift = ffs(value[1]) - 1; in pcs_add_conf2()
886 /* add pinconf setting with 4 parameters */
899 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
907 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
922 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
923 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
924 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, in pcs_parse_pinconf()
925 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
926 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, in pcs_parse_pinconf()
929 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
930 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
931 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
937 return -ENOTSUPP; in pcs_parse_pinconf()
949 return -ENOTSUPP; in pcs_parse_pinconf()
951 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
954 if (!func->conf) in pcs_parse_pinconf()
955 return -ENOMEM; in pcs_parse_pinconf()
956 func->nconfs = nconfs; in pcs_parse_pinconf()
957 conf = &(func->conf[0]); in pcs_parse_pinconf()
959 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
962 return -ENOMEM; in pcs_parse_pinconf()
971 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
972 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
973 m->data.configs.configs = settings; in pcs_parse_pinconf()
974 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
979 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
981 * @np: device node of the mux entry
1003 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
1005 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
1010 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
1011 return -EINVAL; in pcs_parse_one_pinctrl_entry()
1014 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1016 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1018 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1032 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1038 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1049 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1054 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1055 "could not add functions for %pOFn %ux\n", in pcs_parse_one_pinctrl_entry()
1062 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1063 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1064 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1071 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1077 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1078 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1079 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1085 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1092 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1097 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1100 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1102 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1103 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1106 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1117 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1119 int rows, *pins, found = 0, res = -ENOMEM, i, fsel; in pcs_parse_bits_in_pinctrl_entry()
1125 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1126 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1130 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1131 return -ENOTSUPP; in pcs_parse_bits_in_pinctrl_entry()
1134 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1136 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1140 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1142 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1160 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1170 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1176 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1177 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1182 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1191 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1198 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1203 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1204 "could not add functions for %pOFn %ux\n", in pcs_parse_bits_in_pinctrl_entry()
1212 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1213 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1214 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1221 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1225 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1226 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1227 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1230 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1235 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1237 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1238 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1241 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1246 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1263 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1265 return -ENOMEM; in pcs_dt_node_to_map()
1269 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1271 ret = -ENOMEM; in pcs_dt_node_to_map()
1275 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1279 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1287 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1296 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1298 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1304 * pcs_irq_free() - free interrupt
1309 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1311 if (pcs_soc->irq < 0) in pcs_irq_free()
1314 if (pcs->domain) in pcs_irq_free()
1315 irq_domain_remove(pcs->domain); in pcs_irq_free()
1318 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1320 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1324 * pcs_free_resources() - free memory used by this driver
1330 pinctrl_unregister(pcs->pctl); in pcs_free_resources()
1333 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1334 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1340 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1341 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1354 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1356 ret = -ENOMEM; in pcs_add_gpio_func()
1359 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1360 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1361 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1362 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1363 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1364 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1384 * pcs_irq_set() - enables or disables an interrupt
1390 * register that is typically used for wake-up events.
1400 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1405 if (irq != pcswi->irq) in pcs_irq_set()
1408 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1409 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1410 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1415 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1418 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1419 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1422 if (pcs_soc->rearm) in pcs_irq_set()
1423 pcs_soc->rearm(); in pcs_irq_set()
1427 * pcs_irq_mask() - mask pinctrl interrupt
1428 * @d: interrupt data
1434 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1438 * pcs_irq_unmask() - unmask pinctrl interrupt
1439 * @d: interrupt data
1445 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1449 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1450 * @d: interrupt data
1451 * @state: wake-up state
1454 * For runtime PM, the wake-up events should be enabled by default.
1467 * pcs_irq_handle() - common interrupt handler
1471 * mux register. This interrupt is typically used for wake-up events.
1481 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1486 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1487 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1488 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1489 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1490 generic_handle_domain_irq(pcs->domain, in pcs_irq_handle()
1491 pcswi->hwirq); in pcs_irq_handle()
1500 * pcs_irq_handler() - handler for the shared interrupt case
1502 * @d: data
1505 * pinctrl-single share a single interrupt like on omaps.
1515 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1519 * pinctrl-single instance.
1529 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ in pcs_irq_chain_handler()
1536 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1541 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1543 return -ENOMEM; in pcs_irqdomain_map()
1545 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1546 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1547 pcswi->irq = irq; in pcs_irqdomain_map()
1549 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1550 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1551 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1554 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1568 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1575 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1579 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1580 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1581 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1582 return -EINVAL; in pcs_irq_init_chained_handler()
1585 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1586 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1587 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1588 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1589 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1590 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1595 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1600 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1604 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1615 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1617 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1620 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1621 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1622 return -EINVAL; in pcs_irq_init_chained_handler()
1636 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1638 if (!pcs->saved_vals) { in pcs_save_context()
1639 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1640 if (!pcs->saved_vals) in pcs_save_context()
1641 return -ENOMEM; in pcs_save_context()
1644 switch (pcs->width) { in pcs_save_context()
1646 regsl = pcs->saved_vals; in pcs_save_context()
1647 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1648 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1651 regsw = pcs->saved_vals; in pcs_save_context()
1652 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1653 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1656 regshw = pcs->saved_vals; in pcs_save_context()
1657 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1658 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1672 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1674 switch (pcs->width) { in pcs_restore_context()
1676 regsl = pcs->saved_vals; in pcs_restore_context()
1677 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1678 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1681 regsw = pcs->saved_vals; in pcs_restore_context()
1682 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1683 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1686 regshw = pcs->saved_vals; in pcs_restore_context()
1687 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1688 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1700 return -EINVAL; in pinctrl_single_suspend()
1702 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend()
1710 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend()
1719 return -EINVAL; in pinctrl_single_resume()
1721 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume()
1724 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume()
1729 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1734 * Handle legacy binding with no #pinctrl-cells. This should be
1735 * always two pinctrl-single,bit-per-mux and one for others.
1743 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1751 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1754 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1756 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1758 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1759 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1760 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1761 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1762 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1764 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1765 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1766 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1768 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1771 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1779 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1786 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1788 return -EINVAL; in pcs_probe()
1790 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1792 return -ENOMEM; in pcs_probe()
1794 pcs->dev = &pdev->dev; in pcs_probe()
1795 pcs->np = np; in pcs_probe()
1796 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1797 mutex_init(&pcs->mutex); in pcs_probe()
1798 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1799 pcs->flags = soc->flags; in pcs_probe()
1800 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1802 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1803 &pcs->width); in pcs_probe()
1805 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1810 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1811 &pcs->fmask); in pcs_probe()
1813 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1814 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1816 /* If mask property doesn't exist, function mux is invalid. */ in pcs_probe()
1817 pcs->fmask = 0; in pcs_probe()
1818 pcs->fshift = 0; in pcs_probe()
1819 pcs->fmax = 0; in pcs_probe()
1822 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1823 &pcs->foff); in pcs_probe()
1825 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1827 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1828 "pinctrl-single,bit-per-mux"); in pcs_probe()
1830 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1832 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1839 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1840 return -ENODEV; in pcs_probe()
1843 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1845 if (!pcs->res) { in pcs_probe()
1846 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1847 return -EBUSY; in pcs_probe()
1850 pcs->size = resource_size(pcs->res); in pcs_probe()
1851 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1852 if (!pcs->base) { in pcs_probe()
1853 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1854 return -ENODEV; in pcs_probe()
1859 switch (pcs->width) { in pcs_probe()
1861 pcs->read = pcs_readb; in pcs_probe()
1862 pcs->write = pcs_writeb; in pcs_probe()
1865 pcs->read = pcs_readw; in pcs_probe()
1866 pcs->write = pcs_writew; in pcs_probe()
1869 pcs->read = pcs_readl; in pcs_probe()
1870 pcs->write = pcs_writel; in pcs_probe()
1876 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1877 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1878 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1880 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1881 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1887 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); in pcs_probe()
1889 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1897 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1898 if (pcs->socdata.irq) in pcs_probe()
1899 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1902 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1904 if (pdata->rearm) in pcs_probe()
1905 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1906 if (pdata->irq) { in pcs_probe()
1907 pcs->socdata.irq = pdata->irq; in pcs_probe()
1908 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1915 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1918 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1920 return pinctrl_enable(pcs->pctl); in pcs_probe()
1970 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1971 { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1972 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1973 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1974 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1975 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1976 { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
1977 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1978 { .compatible = "pinconf-single", .data = &pinconf_single },
1999 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");