Lines Matching +full:mux +full:- +full:ctrl +full:- +full:list
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
93 { .offset = -1 }, \
94 { .offset = -1 }, \
95 { .offset = -1 }, \
96 { .offset = -1 }, \
99 { .drv_type = type0, .offset = -1 }, \
100 { .drv_type = type1, .offset = -1 }, \
101 { .drv_type = type2, .offset = -1 }, \
102 { .drv_type = type3, .offset = -1 }, \
114 { .type = iom0, .offset = -1 }, \
115 { .type = iom1, .offset = -1 }, \
116 { .type = iom2, .offset = -1 }, \
117 { .type = iom3, .offset = -1 }, \
133 { .offset = -1 }, \
134 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
139 { .drv_type = drv0, .offset = -1 }, \
140 { .drv_type = drv1, .offset = -1 }, \
141 { .drv_type = drv2, .offset = -1 }, \
142 { .drv_type = drv3, .offset = -1 }, \
174 { .type = iom0, .offset = -1 }, \
175 { .type = iom1, .offset = -1 }, \
176 { .type = iom2, .offset = -1 }, \
177 { .type = iom3, .offset = -1 }, \
198 { .type = iom0, .offset = -1 }, \
199 { .type = iom1, .offset = -1 }, \
200 { .type = iom2, .offset = -1 }, \
201 { .type = iom3, .offset = -1 }, \
249 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
250 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
251 return &info->groups[i]; in pinctrl_name_to_group()
264 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
266 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
276 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
280 if (b->bank_num == num) in bank_num_to_bank()
284 return ERR_PTR(-EINVAL); in bank_num_to_bank()
295 return info->ngroups; in rockchip_get_groups_count()
303 return info->groups[selector].name; in rockchip_get_group_name()
312 if (selector >= info->ngroups) in rockchip_get_group_pins()
313 return -EINVAL; in rockchip_get_group_pins()
315 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
316 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
327 struct device *dev = info->dev; in rockchip_dt_node_to_map()
337 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
340 return -EINVAL; in rockchip_dt_node_to_map()
343 map_num += grp->npins; in rockchip_dt_node_to_map()
347 return -ENOMEM; in rockchip_dt_node_to_map()
352 /* create mux map */ in rockchip_dt_node_to_map()
356 return -EINVAL; in rockchip_dt_node_to_map()
359 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
360 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
365 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
368 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
369 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
370 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
374 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
660 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
661 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux() local
665 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
666 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
667 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
668 data->pin == pin) in rockchip_get_recalced_mux()
672 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
675 *reg = data->reg; in rockchip_get_recalced_mux()
676 *mask = data->mask; in rockchip_get_recalced_mux()
677 *bit = data->bit; in rockchip_get_recalced_mux()
681 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
682 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
683 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
684 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
685 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
686 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
687 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
688 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
689 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
690 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
691 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
692 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
693 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
694 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
695 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
696 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
697 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
698 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
699 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
700 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
701 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
702 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
703 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
704 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
705 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
706 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
707 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
708 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
709 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
710 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
711 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
712 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
713 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
714 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
715 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
716 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
717 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
718 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
719 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
720 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
721 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
722 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
723 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
724 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
725 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
726 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
727 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
728 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
829 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
830 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
831 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
832 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
833 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
834 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
835 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
839 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
840 …UTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
844 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
845 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
846 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
847 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
848 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
849 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
850 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
851 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
852 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
853 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
854 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
855 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
856 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
857 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
858 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
859 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
860 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
861 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
876 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
877 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
878 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
879 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
880 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
881 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
882 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
883 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
901 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
902 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
922 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
923 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
924 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
925 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
926 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
927 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
928 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
929 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
930 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
931 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
932 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
933 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
934 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
935 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
936 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
937 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
938 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
939 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
940 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
941 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
942 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
943 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
944 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
945 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
946 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
947 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
948 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
949 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
950 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
951 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
952 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
953 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
954 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
955 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
956 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
957 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
958 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
959 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
960 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
961 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
962 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
963 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
964 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
965 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
966 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
967 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
968 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
969 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
970 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
971 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
972 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
973 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
974 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
975 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
976 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
977 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
978 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
979 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
980 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
981 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
982 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
983 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
984 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
985 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
986 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
987 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
988 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
989 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
990 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
991 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
992 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
993 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
994 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
995 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
996 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
997 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
998 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
999 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1000 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1001 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1002 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1003 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1004 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1005 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1006 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1007 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1008 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1009 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1010 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1011 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1012 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1013 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1014 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1018 int mux, u32 *loc, u32 *reg, u32 *value) in rockchip_get_mux_route() argument
1020 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1021 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route() local
1025 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1026 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1027 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1028 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1032 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1035 *loc = data->route_location; in rockchip_get_mux_route()
1036 *reg = data->route_offset; in rockchip_get_mux_route()
1037 *value = data->route_val; in rockchip_get_mux_route()
1044 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1045 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux() local
1053 return -EINVAL; in rockchip_get_mux()
1055 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1056 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1057 return -EINVAL; in rockchip_get_mux()
1060 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1063 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1064 regmap = info->regmap_pmu; in rockchip_get_mux()
1065 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_get_mux()
1066 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1068 regmap = info->regmap_base; in rockchip_get_mux()
1070 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_get_mux()
1071 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1072 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1088 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1091 if (ctrl->type == RK3588) { in rockchip_get_mux()
1092 if (bank->bank_num == 0) { in rockchip_get_mux()
1096 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1105 regmap = info->regmap_base; in rockchip_get_mux()
1107 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1120 int pin, int mux) in rockchip_verify_mux() argument
1122 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1123 struct device *dev = info->dev; in rockchip_verify_mux()
1127 return -EINVAL; in rockchip_verify_mux()
1129 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1131 return -EINVAL; in rockchip_verify_mux()
1134 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1135 if (mux != RK_FUNC_GPIO) { in rockchip_verify_mux()
1136 dev_err(dev, "pin %d only supports a gpio mux\n", pin); in rockchip_verify_mux()
1137 return -ENOTSUPP; in rockchip_verify_mux()
1145 * Set a new mux function for a pin.
1155 * @mux: new mux function to set
1157 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
1159 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1160 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_mux() local
1161 struct device *dev = info->dev; in rockchip_set_mux()
1168 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
1172 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1175 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rockchip_set_mux()
1177 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1178 regmap = info->regmap_pmu; in rockchip_set_mux()
1179 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_set_mux()
1180 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1182 regmap = info->regmap_base; in rockchip_set_mux()
1184 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_set_mux()
1185 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1186 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1202 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1205 if (ctrl->type == RK3588) { in rockchip_set_mux()
1206 if (bank->bank_num == 0) { in rockchip_set_mux()
1208 if (mux < 8) { in rockchip_set_mux()
1209 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1212 data |= (mux & mask) << bit; in rockchip_set_mux()
1217 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1226 data |= mux << bit; in rockchip_set_mux()
1227 regmap = info->regmap_base; in rockchip_set_mux()
1233 data |= (mux & mask) << bit; in rockchip_set_mux()
1237 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1242 if (mux > mask) in rockchip_set_mux()
1243 return -EINVAL; in rockchip_set_mux()
1245 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1246 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
1253 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1256 route_regmap = info->regmap_base; in rockchip_set_mux()
1268 data |= (mux & mask) << bit; in rockchip_set_mux()
1284 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1287 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1288 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1291 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1295 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1296 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1316 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1319 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1320 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1323 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1327 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1328 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1349 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1352 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1353 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1357 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1360 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1379 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1382 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1383 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1387 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1389 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1390 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1410 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1413 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1414 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1417 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1421 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1422 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1443 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1446 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1447 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1451 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1454 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1473 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_pull_reg_and_bit()
1476 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1478 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1480 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); in rv1126_calc_pull_reg_and_bit()
1485 *regmap = info->regmap_pmu; in rv1126_calc_pull_reg_and_bit()
1489 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1490 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; in rv1126_calc_pull_reg_and_bit()
1510 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_drv_reg_and_bit()
1513 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1515 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1517 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); in rv1126_calc_drv_reg_and_bit()
1518 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1523 *regmap = info->regmap_pmu; in rv1126_calc_drv_reg_and_bit()
1526 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1528 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; in rv1126_calc_drv_reg_and_bit()
1549 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_schmitt_reg_and_bit()
1552 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1554 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1556 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); in rv1126_calc_schmitt_reg_and_bit()
1560 *regmap = info->regmap_pmu; in rv1126_calc_schmitt_reg_and_bit()
1564 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1567 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; in rv1126_calc_schmitt_reg_and_bit()
1583 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1585 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1588 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1603 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1605 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1607 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1621 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1623 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1625 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1643 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1646 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1647 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1648 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1649 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1654 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1655 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1656 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1659 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1660 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1668 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1680 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1683 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1684 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1691 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1695 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1696 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1716 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1719 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1720 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1727 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1731 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1732 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1748 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1750 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1752 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1767 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1769 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1771 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1786 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1788 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1790 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1805 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1807 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1809 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1825 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1828 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1829 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1836 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1840 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1841 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1858 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1861 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1862 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1869 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
1873 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1874 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
1892 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
1895 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1896 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
1899 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1905 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
1909 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1910 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1924 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
1928 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1929 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
1931 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
1933 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
1934 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
1935 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
1953 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
1955 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
1956 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
1958 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1964 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
1966 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1986 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
1989 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
1990 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
1997 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
1999 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
2121 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_pull_reg_and_bit()
2122 u8 bank_num = bank->bank_num; in rk3588_calc_pull_reg_and_bit()
2126 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2129 *regmap = info->regmap_base; in rk3588_calc_pull_reg_and_bit()
2136 return -EINVAL; in rk3588_calc_pull_reg_and_bit()
2146 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_drv_reg_and_bit()
2147 u8 bank_num = bank->bank_num; in rk3588_calc_drv_reg_and_bit()
2151 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2154 *regmap = info->regmap_base; in rk3588_calc_drv_reg_and_bit()
2161 return -EINVAL; in rk3588_calc_drv_reg_and_bit()
2172 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_schmitt_reg_and_bit()
2173 u8 bank_num = bank->bank_num; in rk3588_calc_schmitt_reg_and_bit()
2177 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2180 *regmap = info->regmap_base; in rk3588_calc_schmitt_reg_and_bit()
2187 return -EINVAL; in rk3588_calc_schmitt_reg_and_bit()
2191 { 2, 4, 8, 12, -1, -1, -1, -1 },
2192 { 3, 6, 9, 12, -1, -1, -1, -1 },
2193 { 5, 10, 15, 20, -1, -1, -1, -1 },
2201 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2202 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin() local
2203 struct device *dev = info->dev; in rockchip_get_drive_perpin()
2208 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2210 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2224 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
2248 bit -= 16; in rockchip_get_drive_perpin()
2253 return -EINVAL; in rockchip_get_drive_perpin()
2264 return -EINVAL; in rockchip_get_drive_perpin()
2272 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
2280 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2281 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin() local
2282 struct device *dev = info->dev; in rockchip_set_drive_perpin()
2287 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2289 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
2290 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2292 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2295 if (ctrl->type == RK3588) { in rockchip_set_drive_perpin()
2299 } else if (ctrl->type == RK3568) { in rockchip_set_drive_perpin()
2301 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
2305 if (ctrl->type == RV1126) { in rockchip_set_drive_perpin()
2311 ret = -EINVAL; in rockchip_set_drive_perpin()
2337 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2359 bit -= 16; in rockchip_set_drive_perpin()
2364 return -EINVAL; in rockchip_set_drive_perpin()
2374 return -EINVAL; in rockchip_set_drive_perpin()
2379 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2405 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2406 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull() local
2407 struct device *dev = info->dev; in rockchip_get_pull()
2414 if (ctrl->type == RK3066B) in rockchip_get_pull()
2417 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2425 switch (ctrl->type) { in rockchip_get_pull()
2440 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2442 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2444 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_get_pull()
2447 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2455 return -EINVAL; in rockchip_get_pull()
2462 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2463 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull() local
2464 struct device *dev = info->dev; in rockchip_set_pull()
2470 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); in rockchip_set_pull()
2473 if (ctrl->type == RK3066B) in rockchip_set_pull()
2474 return pull ? -EINVAL : 0; in rockchip_set_pull()
2476 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2480 switch (ctrl->type) { in rockchip_set_pull()
2498 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2499 ret = -EINVAL; in rockchip_set_pull()
2508 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_set_pull()
2511 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2522 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2530 return -EINVAL; in rockchip_set_pull()
2546 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2548 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2551 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2569 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
2571 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2572 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
2575 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
2577 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
2589 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2590 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt() local
2596 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2605 switch (ctrl->type) { in rockchip_get_schmitt()
2607 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
2618 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2619 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt() local
2620 struct device *dev = info->dev; in rockchip_set_schmitt()
2626 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2627 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2629 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2634 switch (ctrl->type) { in rockchip_set_schmitt()
2636 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
2657 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2665 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2674 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2675 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2684 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2685 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2686 struct device *dev = info->dev; in rockchip_pmx_set()
2691 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2697 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2699 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2707 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2708 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2725 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); in rockchip_pmx_gpio_set_direction()
2740 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, in rockchip_pinconf_pull_valid() argument
2743 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2773 return -ENOMEM; in rockchip_pinconf_defer_pin()
2775 cfg->pin = pin; in rockchip_pinconf_defer_pin()
2776 cfg->param = param; in rockchip_pinconf_defer_pin()
2777 cfg->arg = arg; in rockchip_pinconf_defer_pin()
2779 list_add_tail(&cfg->head, &bank->deferred_pins); in rockchip_pinconf_defer_pin()
2790 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_set()
2803 * The lock makes sure that either gpio-probe has completed in rockchip_pinconf_set()
2806 mutex_lock(&bank->deferred_lock); in rockchip_pinconf_set()
2807 if (!gpio || !gpio->direction_output) { in rockchip_pinconf_set()
2808 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, in rockchip_pinconf_set()
2810 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2816 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2821 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2830 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2831 return -ENOTSUPP; in rockchip_pinconf_set()
2834 return -EINVAL; in rockchip_pinconf_set()
2836 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2842 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2845 return -EINVAL; in rockchip_pinconf_set()
2847 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
2853 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2856 return -EINVAL; in rockchip_pinconf_set()
2858 rc = gpio->direction_input(gpio, pin - bank->pin_base); in rockchip_pinconf_set()
2863 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2864 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2865 return -ENOTSUPP; in rockchip_pinconf_set()
2868 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2873 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2874 return -ENOTSUPP; in rockchip_pinconf_set()
2877 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2882 return -ENOTSUPP; in rockchip_pinconf_set()
2896 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_get()
2903 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2904 return -EINVAL; in rockchip_pinconf_get()
2912 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2913 return -ENOTSUPP; in rockchip_pinconf_get()
2915 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2916 return -EINVAL; in rockchip_pinconf_get()
2921 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2923 return -EINVAL; in rockchip_pinconf_get()
2925 if (!gpio || !gpio->get) { in rockchip_pinconf_get()
2930 rc = gpio->get(gpio, pin - bank->pin_base); in rockchip_pinconf_get()
2937 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2938 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2939 return -ENOTSUPP; in rockchip_pinconf_get()
2941 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2948 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2949 return -ENOTSUPP; in rockchip_pinconf_get()
2951 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2958 return -ENOTSUPP; in rockchip_pinconf_get()
2974 { .compatible = "rockchip,gpio-bank" },
2975 { .compatible = "rockchip,rk3188-gpio-bank0" },
2988 info->nfunctions++; in rockchip_pinctrl_child_count()
2989 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
2998 struct device *dev = info->dev; in rockchip_pinctrl_parse_groups()
3001 const __be32 *list; in rockchip_pinctrl_parse_groups() local
3009 grp->name = np->name; in rockchip_pinctrl_parse_groups()
3012 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
3015 list = of_get_property(np, "rockchip,pins", &size); in rockchip_pinctrl_parse_groups()
3017 size /= sizeof(*list); in rockchip_pinctrl_parse_groups()
3019 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
3021 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
3023 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3024 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3025 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
3026 return -ENOMEM; in rockchip_pinctrl_parse_groups()
3032 num = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3037 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3038 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3040 phandle = list++; in rockchip_pinctrl_parse_groups()
3042 return -EINVAL; in rockchip_pinctrl_parse_groups()
3046 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
3059 struct device *dev = info->dev; in rockchip_pinctrl_parse_functions()
3069 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
3072 func->name = np->name; in rockchip_pinctrl_parse_functions()
3073 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
3074 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3077 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
3078 if (!func->groups) in rockchip_pinctrl_parse_functions()
3079 return -ENOMEM; in rockchip_pinctrl_parse_functions()
3082 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
3083 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
3097 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
3098 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
3105 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
3106 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
3108 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3109 if (!info->functions) in rockchip_pinctrl_parse_dt()
3110 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3112 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3113 if (!info->groups) in rockchip_pinctrl_parse_dt()
3114 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3136 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
3139 struct device *dev = &pdev->dev; in rockchip_pinctrl_register()
3144 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
3145 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
3146 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
3147 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
3148 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
3150 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); in rockchip_pinctrl_register()
3152 return -ENOMEM; in rockchip_pinctrl_register()
3154 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
3155 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
3158 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3159 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3161 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); in rockchip_pinctrl_register()
3165 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3166 pdesc->number = k; in rockchip_pinctrl_register()
3167 pdesc->name = pin_names[pin]; in rockchip_pinctrl_register()
3171 INIT_LIST_HEAD(&pin_bank->deferred_pins); in rockchip_pinctrl_register()
3172 mutex_init(&pin_bank->deferred_lock); in rockchip_pinctrl_register()
3179 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); in rockchip_pinctrl_register()
3180 if (IS_ERR(info->pctl_dev)) in rockchip_pinctrl_register()
3181 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
3193 struct device *dev = &pdev->dev; in rockchip_pinctrl_get_soc_data()
3194 struct device_node *node = dev->of_node; in rockchip_pinctrl_get_soc_data()
3196 struct rockchip_pin_ctrl *ctrl; in rockchip_pinctrl_get_soc_data() local
3201 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3203 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3204 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3205 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3206 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3207 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3208 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3211 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3212 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3213 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3214 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3218 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3219 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3222 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3226 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3227 if ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3228 (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3229 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3231 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3233 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3234 (iom->type & IOMUX_L_SOURCE_PMU)) ? in rockchip_pinctrl_get_soc_data()
3239 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3240 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3241 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3243 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3245 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3250 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3256 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3259 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3266 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3268 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3269 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3274 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3282 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3283 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3286 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3287 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3288 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3292 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3293 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3296 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3297 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3298 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3303 return ctrl; in rockchip_pinctrl_get_soc_data()
3314 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3320 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save in rockchip_pinctrl_suspend()
3323 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3324 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3327 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3340 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
3341 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3348 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3357 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3358 struct device_node *np = dev->of_node, *node; in rockchip_pinctrl_probe()
3359 struct rockchip_pin_ctrl *ctrl; in rockchip_pinctrl_probe() local
3364 if (!dev->of_node) in rockchip_pinctrl_probe()
3365 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); in rockchip_pinctrl_probe()
3369 return -ENOMEM; in rockchip_pinctrl_probe()
3371 info->dev = dev; in rockchip_pinctrl_probe()
3373 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); in rockchip_pinctrl_probe()
3374 if (!ctrl) in rockchip_pinctrl_probe()
3375 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); in rockchip_pinctrl_probe()
3376 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3380 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3382 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3383 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3389 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3391 info->regmap_base = in rockchip_pinctrl_probe()
3394 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3395 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3398 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3403 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3404 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3405 info->regmap_pull = in rockchip_pinctrl_probe()
3413 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3415 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3416 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3425 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); in rockchip_pinctrl_probe()
3439 of_platform_depopulate(&pdev->dev); in rockchip_pinctrl_remove()
3441 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
3442 bank = &info->ctrl->pin_banks[i]; in rockchip_pinctrl_remove()
3444 mutex_lock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3445 while (!list_empty(&bank->deferred_pins)) { in rockchip_pinctrl_remove()
3446 cfg = list_first_entry(&bank->deferred_pins, in rockchip_pinctrl_remove()
3448 list_del(&cfg->head); in rockchip_pinctrl_remove()
3451 mutex_unlock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3481 .label = "PX30-GPIO",
3505 .label = "RV1108-GPIO",
3545 .label = "RV1126-GPIO",
3547 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3568 .label = "RK2928-GPIO",
3583 .label = "RK3036-GPIO",
3601 .label = "RK3066a-GPIO",
3617 .label = "RK3066b-GPIO",
3632 .label = "RK3128-GPIO",
3652 .label = "RK3188-GPIO",
3670 .label = "RK3228-GPIO",
3714 .label = "RK3288-GPIO",
3750 .label = "RK3308-GPIO",
3779 .label = "RK3328-GPIO",
3805 .label = "RK3368-GPIO",
3825 -1,
3826 -1,
3869 .label = "RK3399-GPIO",
3907 .label = "RK3568-GPIO",
3936 .label = "RK3588-GPIO",
3944 { .compatible = "rockchip,px30-pinctrl",
3946 { .compatible = "rockchip,rv1108-pinctrl",
3948 { .compatible = "rockchip,rv1126-pinctrl",
3950 { .compatible = "rockchip,rk2928-pinctrl",
3952 { .compatible = "rockchip,rk3036-pinctrl",
3954 { .compatible = "rockchip,rk3066a-pinctrl",
3956 { .compatible = "rockchip,rk3066b-pinctrl",
3958 { .compatible = "rockchip,rk3128-pinctrl",
3960 { .compatible = "rockchip,rk3188-pinctrl",
3962 { .compatible = "rockchip,rk3228-pinctrl",
3964 { .compatible = "rockchip,rk3288-pinctrl",
3966 { .compatible = "rockchip,rk3308-pinctrl",
3968 { .compatible = "rockchip,rk3328-pinctrl",
3970 { .compatible = "rockchip,rk3368-pinctrl",
3972 { .compatible = "rockchip,rk3399-pinctrl",
3974 { .compatible = "rockchip,rk3568-pinctrl",
3976 { .compatible = "rockchip,rk3588-pinctrl",
3985 .name = "rockchip-pinctrl",
4005 MODULE_ALIAS("platform:pinctrl-rockchip");