Lines Matching +full:0 +full:x184
53 #define IOMUX_GPIO_ONLY BIT(0)
119 .pull_type[0] = pull0, \
144 .pull_type[0] = pull0, \
209 .pull_type[0] = pull0, \
249 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
318 return 0; in rockchip_get_group_pins()
358 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; in rockchip_dt_node_to_map()
359 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
360 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
365 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
376 return 0; in rockchip_dt_node_to_map()
400 .pin = 0,
401 .reg = 0x418,
402 .bit = 0,
403 .mask = 0x3
407 .reg = 0x418,
409 .mask = 0x3
413 .reg = 0x418,
415 .mask = 0x3
419 .reg = 0x418,
421 .mask = 0x3
425 .reg = 0x418,
427 .mask = 0x3
431 .reg = 0x418,
433 .mask = 0x3
437 .reg = 0x418,
439 .mask = 0x3
443 .reg = 0x418,
445 .mask = 0x3
449 .reg = 0x41c,
450 .bit = 0,
451 .mask = 0x3
455 .reg = 0x41c,
457 .mask = 0x3
463 .num = 0,
465 .reg = 0x10000,
466 .bit = 0,
467 .mask = 0xf
470 .num = 0,
472 .reg = 0x10000,
474 .mask = 0xf
477 .num = 0,
479 .reg = 0x10000,
481 .mask = 0xf
484 .num = 0,
486 .reg = 0x10000,
488 .mask = 0xf
496 .reg = 0xe8,
497 .bit = 0,
498 .mask = 0x7
502 .reg = 0xe8,
504 .mask = 0x7
508 .reg = 0xe8,
510 .mask = 0x7
514 .reg = 0xe8,
516 .mask = 0x7
520 .reg = 0xd4,
522 .mask = 0x7
531 .reg = 0x28,
533 .mask = 0xf
538 .reg = 0x2c,
539 .bit = 0,
540 .mask = 0x3
545 .reg = 0x30,
547 .mask = 0xf
552 .reg = 0x30,
554 .mask = 0xf
559 .reg = 0x30,
561 .mask = 0xf
566 .reg = 0x34,
567 .bit = 0,
568 .mask = 0xf
573 .reg = 0x34,
575 .mask = 0xf
580 .reg = 0x34,
582 .mask = 0xf
587 .reg = 0x40,
589 .mask = 0x3
594 .reg = 0x40,
596 .mask = 0x3
601 .reg = 0x50,
602 .bit = 0,
603 .mask = 0x3
608 .reg = 0x68,
610 .mask = 0x3
615 .reg = 0x68,
617 .mask = 0x3
622 .reg = 0x68,
624 .mask = 0xf
629 .reg = 0x68,
631 .mask = 0xf
639 .reg = 0x24,
641 .mask = 0x3
645 .reg = 0x28,
646 .bit = 0,
647 .mask = 0x7
651 .reg = 0x30,
653 .mask = 0x3
665 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
681 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
682 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
683 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
684 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
685 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
686 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
687 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
688 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
689 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
690 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
691 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
692 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
693 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
694 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
695 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
696 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
697 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
698 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
699 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
700 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
701 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
702 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
703 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
704 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
705 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
706 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
707 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
708 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
709 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
710 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
711 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
712 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
713 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
714 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
715 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
716 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
717 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
718 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
719 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
720 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
721 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
722 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
723 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
724 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
725 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
726 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
727 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
728 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
732 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
733 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
735 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
736 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
737 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
739 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
740 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
742 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
743 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
745 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
746 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
748 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
749 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
750 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
752 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
753 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
755 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
756 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
757 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
759 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
760 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
761 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
763 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
764 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
766 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
767 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
769 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
770 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
772 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
773 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
775 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
776 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
778 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
779 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
781 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
782 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
784 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
785 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
786 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
788 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
789 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
790 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
792 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
793 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
794 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
796 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
797 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
799 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
800 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
802 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
803 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
805 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
806 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
808 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
809 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
811 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
812 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
814 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
815 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
817 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
818 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
820 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
821 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
822 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
824 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
825 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
829 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
830 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
831 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
832 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
833 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
834 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
835 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
839 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
840 …RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on em…
844 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
845 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
846 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
847 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
848 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
849 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
850 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
851 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
852 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
853 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
854 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
855 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
856 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
857 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
858 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
859 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
860 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
861 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
865 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
866 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
870 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
871 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
872 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
873 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
874 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
875 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
876 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
877 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
878 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
879 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
880 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
881 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
882 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
883 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
884 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
885 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
886 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
887 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
888 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
889 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
890 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
891 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
892 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
893 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
894 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
895 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
899 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
900 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
901 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
902 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
903 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
904 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
905 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
906 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
907 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
908 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
909 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
910 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
914 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
915 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
916 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
917 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
918 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
922 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
923 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
924 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
925 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
926 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
927 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
928 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
929 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
930 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
931 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
932 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
933 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
934 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
935 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
936 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
937 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
938 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
939 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
940 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
941 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
942 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
943 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
944 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
945 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
946 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
947 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
948 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
949 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
950 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
951 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
952 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
953 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
954 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
955 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
956 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
957 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
958 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
959 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
960 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
961 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
962 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
963 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
964 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
965 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
966 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
967 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
968 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
969 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
970 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
971 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
972 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
973 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
974 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
975 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
976 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
977 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
978 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
979 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
980 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
981 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
982 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
983 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
984 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
985 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
986 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
987 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
988 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
989 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
990 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
991 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
992 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
993 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
994 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
995 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
996 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
997 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
998 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
999 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1000 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1001 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1002 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1003 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1004 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1005 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1006 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1007 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1008 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1009 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1010 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1011 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1012 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1013 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1014 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1025 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1075 reg += 0x4; in rockchip_get_mux()
1077 mask = 0xf; in rockchip_get_mux()
1080 reg += 0x4; in rockchip_get_mux()
1082 mask = 0x7; in rockchip_get_mux()
1085 mask = 0x3; in rockchip_get_mux()
1092 if (bank->bank_num == 0) { in rockchip_get_mux()
1094 u32 reg0 = 0; in rockchip_get_mux()
1096 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1104 reg = reg + 0x8000; /* BUS_IOC_BASE */ in rockchip_get_mux()
1107 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1108 reg += 0x8000; /* BUS_IOC_BASE */ in rockchip_get_mux()
1141 return 0; in rockchip_verify_mux()
1169 if (ret < 0) in rockchip_set_mux()
1173 return 0; in rockchip_set_mux()
1189 reg += 0x4; in rockchip_set_mux()
1191 mask = 0xf; in rockchip_set_mux()
1194 reg += 0x4; in rockchip_set_mux()
1196 mask = 0x7; in rockchip_set_mux()
1199 mask = 0x3; in rockchip_set_mux()
1206 if (bank->bank_num == 0) { in rockchip_set_mux()
1209 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1215 u32 reg0 = 0; in rockchip_set_mux()
1217 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1223 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ in rockchip_set_mux()
1237 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1238 reg += 0x8000; /* BUS_IOC_BASE */ in rockchip_set_mux()
1274 #define PX30_PULL_PMU_OFFSET 0x10
1275 #define PX30_PULL_GRF_OFFSET 0x60
1287 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1295 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1303 return 0; in px30_calc_pull_reg_and_bit()
1306 #define PX30_DRV_PMU_OFFSET 0x20
1307 #define PX30_DRV_GRF_OFFSET 0xf0
1319 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1327 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1335 return 0; in px30_calc_drv_reg_and_bit()
1338 #define PX30_SCHMITT_PMU_OFFSET 0x38
1339 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1352 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1366 return 0; in px30_calc_schmitt_reg_and_bit()
1369 #define RV1108_PULL_PMU_OFFSET 0x10
1370 #define RV1108_PULL_OFFSET 0x110
1382 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1389 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1397 return 0; in rv1108_calc_pull_reg_and_bit()
1400 #define RV1108_DRV_PMU_OFFSET 0x20
1401 #define RV1108_DRV_GRF_OFFSET 0x210
1413 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1421 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1429 return 0; in rv1108_calc_drv_reg_and_bit()
1432 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1433 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1446 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1459 return 0; in rv1108_calc_schmitt_reg_and_bit()
1462 #define RV1126_PULL_PMU_OFFSET 0x40
1463 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1476 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1483 return 0; in rv1126_calc_pull_reg_and_bit()
1497 return 0; in rv1126_calc_pull_reg_and_bit()
1500 #define RV1126_DRV_PMU_OFFSET 0x20
1501 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1513 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1518 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1521 return 0; in rv1126_calc_drv_reg_and_bit()
1535 return 0; in rv1126_calc_drv_reg_and_bit()
1538 #define RV1126_SCHMITT_PMU_OFFSET 0x60
1539 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1552 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1558 return 0; in rv1126_calc_schmitt_reg_and_bit()
1572 return 0; in rv1126_calc_schmitt_reg_and_bit()
1577 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1592 return 0; in rk3308_calc_schmitt_reg_and_bit()
1595 #define RK2928_PULL_OFFSET 0x118
1612 return 0; in rk2928_calc_pull_reg_and_bit()
1615 #define RK3128_PULL_OFFSET 0x118
1630 return 0; in rk3128_calc_pull_reg_and_bit()
1633 #define RK3188_PULL_OFFSET 0x164
1637 #define RK3188_PULL_PMU_OFFSET 0x64
1646 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1649 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1656 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1666 * pin in bits 1:0 in rk3188_calc_pull_reg_and_bit()
1672 return 0; in rk3188_calc_pull_reg_and_bit()
1675 #define RK3288_PULL_OFFSET 0x140
1683 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1695 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1703 return 0; in rk3288_calc_pull_reg_and_bit()
1706 #define RK3288_DRV_PMU_OFFSET 0x70
1707 #define RK3288_DRV_GRF_OFFSET 0x1c0
1719 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1731 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1739 return 0; in rk3288_calc_drv_reg_and_bit()
1742 #define RK3228_PULL_OFFSET 0x100
1758 return 0; in rk3228_calc_pull_reg_and_bit()
1761 #define RK3228_DRV_GRF_OFFSET 0x200
1777 return 0; in rk3228_calc_drv_reg_and_bit()
1780 #define RK3308_PULL_OFFSET 0xa0
1796 return 0; in rk3308_calc_pull_reg_and_bit()
1799 #define RK3308_DRV_GRF_OFFSET 0x100
1815 return 0; in rk3308_calc_drv_reg_and_bit()
1818 #define RK3368_PULL_GRF_OFFSET 0x100
1819 #define RK3368_PULL_PMU_OFFSET 0x10
1828 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1840 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1848 return 0; in rk3368_calc_pull_reg_and_bit()
1851 #define RK3368_DRV_PMU_OFFSET 0x20
1852 #define RK3368_DRV_GRF_OFFSET 0x200
1861 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1873 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1881 return 0; in rk3368_calc_drv_reg_and_bit()
1884 #define RK3399_PULL_GRF_OFFSET 0xe040
1885 #define RK3399_PULL_PMU_OFFSET 0x40
1895 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1909 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1917 return 0; in rk3399_calc_pull_reg_and_bit()
1928 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1940 return 0; in rk3399_calc_drv_reg_and_bit()
1943 #define RK3568_PULL_PMU_OFFSET 0x20
1944 #define RK3568_PULL_GRF_OFFSET 0x80
1947 #define RK3568_PULL_BANK_STRIDE 0x10
1955 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
1973 return 0; in rk3568_calc_pull_reg_and_bit()
1976 #define RK3568_DRV_PMU_OFFSET 0x70
1977 #define RK3568_DRV_GRF_OFFSET 0x200
1980 #define RK3568_DRV_BANK_STRIDE 0x40
1989 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
2006 return 0; in rk3568_calc_drv_reg_and_bit()
2009 #define RK3588_PMU1_IOC_REG (0x0000)
2010 #define RK3588_PMU2_IOC_REG (0x4000)
2011 #define RK3588_BUS_IOC_REG (0x8000)
2012 #define RK3588_VCCIO1_4_IOC_REG (0x9000)
2013 #define RK3588_VCCIO3_5_IOC_REG (0xA000)
2014 #define RK3588_VCCIO2_IOC_REG (0xB000)
2015 #define RK3588_VCCIO6_IOC_REG (0xC000)
2016 #define RK3588_EMMC_IOC_REG (0xD000)
2019 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2020 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2021 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2022 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2023 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2024 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2025 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2026 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2027 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2028 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2029 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2030 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2031 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2032 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2033 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2034 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2035 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2036 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2037 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2038 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2039 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2040 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2041 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2042 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2043 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2044 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2045 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2046 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2047 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2048 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2049 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2050 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2051 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2052 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2053 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2054 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2055 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2056 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2057 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2058 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2059 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2063 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2064 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2065 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2066 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2067 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2068 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2069 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2070 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2071 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2072 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2073 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2074 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2075 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2076 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2077 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2078 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2079 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2080 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2081 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2082 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2083 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2084 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2085 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2089 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2090 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2091 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2092 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2093 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2094 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2095 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2096 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2097 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2098 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2099 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2100 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2101 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2102 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2103 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2104 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2105 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2106 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2107 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2108 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2109 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2110 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2111 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2126 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2127 if (pin >= rk3588_p_regs[i][0]) { in rk3588_calc_pull_reg_and_bit()
2132 return 0; in rk3588_calc_pull_reg_and_bit()
2151 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2152 if (pin >= rk3588_ds_regs[i][0]) { in rk3588_calc_drv_reg_and_bit()
2157 return 0; in rk3588_calc_drv_reg_and_bit()
2177 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2178 if (pin >= rk3588_smt_regs[i][0]) { in rk3588_calc_schmitt_reg_and_bit()
2183 return 0; in rk3588_calc_schmitt_reg_and_bit()
2219 case 0 ... 12: in rockchip_get_drive_perpin()
2231 ret = regmap_read(regmap, reg + 0x4, &temp); in rockchip_get_drive_perpin()
2236 * the bit data[15] contains bit 0 of the value in rockchip_get_drive_perpin()
2237 * while temp[1:0] contains bits 2 and 1 in rockchip_get_drive_perpin()
2240 temp &= 0x3; in rockchip_get_drive_perpin()
2312 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { in rockchip_set_drive_perpin()
2316 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { in rockchip_set_drive_perpin()
2322 if (ret < 0) { in rockchip_set_drive_perpin()
2332 case 0 ... 12: in rockchip_set_drive_perpin()
2338 * over 2 registers, the bit data[15] contains bit 0 in rockchip_set_drive_perpin()
2339 * of the value while temp[1:0] contains bits 2 and 1 in rockchip_set_drive_perpin()
2341 data = (ret & 0x1) << 15; in rockchip_set_drive_perpin()
2342 temp = (ret >> 0x1) & 0x3; in rockchip_set_drive_perpin()
2350 rmask = 0x3 | (0x3 << 16); in rockchip_set_drive_perpin()
2351 temp |= (0x3 << 16); in rockchip_set_drive_perpin()
2352 reg += 0x4; in rockchip_set_drive_perpin()
2447 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2474 return pull ? -EINVAL : 0; in rockchip_set_pull()
2500 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); in rockchip_set_pull()
2511 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2516 if (ret < 0) { in rockchip_set_pull()
2539 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2555 return 0; in rk3328_calc_schmitt_reg_and_bit()
2560 #define RK3568_SCHMITT_BANK_STRIDE 0x10
2561 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
2562 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2571 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2584 return 0; in rk3568_calc_schmitt_reg_and_bit()
2612 return data & 0x1; in rockchip_get_schmitt()
2638 data |= ((enable ? 0x2 : 0x1) << bit); in rockchip_set_schmitt()
2677 return 0; in rockchip_pmx_get_groups()
2688 int cnt, ret = 0; in rockchip_pmx_set()
2697 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2707 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2708 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2713 return 0; in rockchip_pmx_set()
2781 return 0; in rockchip_pinconf_defer_pin()
2796 for (i = 0; i < num_configs; i++) { in rockchip_pinconf_set()
2869 if (rc < 0) in rockchip_pinconf_set()
2878 if (rc < 0) in rockchip_pinconf_set()
2887 return 0; in rockchip_pinconf_set()
2906 arg = 0; in rockchip_pinconf_get()
2926 arg = 0; in rockchip_pinconf_get()
2931 if (rc < 0) in rockchip_pinconf_get()
2934 arg = rc ? 1 : 0; in rockchip_pinconf_get()
2942 if (rc < 0) in rockchip_pinconf_get()
2952 if (rc < 0) in rockchip_pinconf_get()
2964 return 0; in rockchip_pinconf_get()
3028 for (i = 0, j = 0; i < size; i += 4, j++) { in rockchip_pinctrl_parse_groups()
3052 return 0; in rockchip_pinctrl_parse_groups()
3065 u32 i = 0; in rockchip_pinctrl_parse_functions()
3074 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3075 return 0; in rockchip_pinctrl_parse_functions()
3091 return 0; in rockchip_pinctrl_parse_functions()
3116 i = 0; in rockchip_pinctrl_parse_dt()
3130 return 0; in rockchip_pinctrl_parse_dt()
3158 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3165 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3183 return 0; in rockchip_pinctrl_register()
3208 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3209 int bank_pins = 0; in rockchip_pinctrl_get_soc_data()
3217 for (j = 0; j < 4; j++) { in rockchip_pinctrl_get_soc_data()
3226 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3239 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3249 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3283 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3284 int pin = 0; in rockchip_pinctrl_get_soc_data()
3293 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3294 int pin = 0; in rockchip_pinctrl_get_soc_data()
3306 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3332 return 0; in rockchip_pinctrl_suspend()
3378 node = of_parse_phandle(np, "rockchip,grf", 0); in rockchip_pinctrl_probe()
3385 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_pinctrl_probe()
3398 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3411 node = of_parse_phandle(np, "rockchip,pmu", 0); in rockchip_pinctrl_probe()
3429 return 0; in rockchip_pinctrl_probe()
3441 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
3456 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3483 .grf_mux_offset = 0x0,
3484 .pmu_mux_offset = 0x0,
3493 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3497 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3498 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3499 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3507 .grf_mux_offset = 0x10,
3508 .pmu_mux_offset = 0x0,
3517 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3527 0x10010, 0x10018, 0x10020, 0x10028),
3539 IOMUX_WIDTH_4BIT, 0, 0, 0),
3547 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3548 .pmu_mux_offset = 0x0,
3559 PIN_BANK(0, 32, "gpio0"),
3570 .grf_mux_offset = 0xa8,
3575 PIN_BANK(0, 32, "gpio0"),
3585 .grf_mux_offset = 0xa8,
3590 PIN_BANK(0, 32, "gpio0"),
3603 .grf_mux_offset = 0xa8,
3608 PIN_BANK(0, 32, "gpio0"),
3619 .grf_mux_offset = 0x60,
3623 PIN_BANK(0, 32, "gpio0"),
3634 .grf_mux_offset = 0xa8,
3643 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3654 .grf_mux_offset = 0x60,
3661 PIN_BANK(0, 32, "gpio0"),
3672 .grf_mux_offset = 0x0,
3680 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3688 0
3690 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3691 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3694 0,
3695 0
3698 0,
3699 0,
3702 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3703 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3704 0,
3716 .grf_mux_offset = 0x0,
3717 .pmu_mux_offset = 0x84,
3725 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3752 .grf_mux_offset = 0x0,
3763 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3764 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3765 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3768 0),
3772 0,
3773 0),
3781 .grf_mux_offset = 0x0,
3792 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3807 .grf_mux_offset = 0x0,
3808 .pmu_mux_offset = 0x0,
3814 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3823 0x80,
3824 0x88,
3840 0xa0,
3841 0xa8,
3842 0xb0,
3843 0xb8
3871 .grf_mux_offset = 0xe000,
3872 .pmu_mux_offset = 0x0,
3873 .grf_drv_offset = 0xe100,
3874 .pmu_drv_offset = 0x80,
3882 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3909 .grf_mux_offset = 0x0,
3910 .pmu_mux_offset = 0x0,
3911 .grf_drv_offset = 0x0200,
3912 .pmu_drv_offset = 0x0070,
3921 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",