Lines Matching +full:mux +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0
24 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/platform_data/x86/pwm-lpss.h>
31 #include "pinctrl-intel.h"
108 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
109 #define padgroup_offset(g, p) ((p) - (g)->base)
116 for (i = 0; i < pctrl->ncommunities; i++) { in intel_get_community()
117 community = &pctrl->communities[i]; in intel_get_community()
118 if (pin >= community->pin_base && in intel_get_community()
119 pin < community->pin_base + community->npins) in intel_get_community()
123 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); in intel_get_community()
134 for (i = 0; i < community->ngpps; i++) { in intel_community_get_padgroup()
135 const struct intel_padgroup *padgrp = &community->gpps[i]; in intel_community_get_padgroup()
137 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) in intel_community_get_padgroup()
156 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; in intel_get_padcfg()
161 return community->pad_regs + reg + padno * nregs * 4; in intel_get_padcfg()
174 if (!community->padown_offset) in intel_pad_owned_by_host()
183 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; in intel_pad_owned_by_host()
184 padown = community->regs + offset; in intel_pad_owned_by_host()
199 if (!community->hostown_offset) in intel_pad_acpi_mode()
207 offset = community->hostown_offset + padgrp->reg_num * 4; in intel_pad_acpi_mode()
208 hostown = community->regs + offset; in intel_pad_acpi_mode()
214 * enum - Locking variants of the pad configuration
217 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
218 * @PAD_LOCKED_TX: pad configuration TX state is locked
219 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
221 * Locking is considered as read-only mode for corresponding registers and
222 * their respective fields. That said, TX state bit is locked separately from
243 if (!community->padcfglock_offset) in intel_pad_locked()
255 * either fully or partially locked. in intel_pad_locked()
257 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; in intel_pad_locked()
258 value = readl(community->regs + offset); in intel_pad_locked()
262 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; in intel_pad_locked()
263 value = readl(community->regs + offset); in intel_pad_locked()
284 return pctrl->soc->ngroups; in intel_get_groups_count()
292 return pctrl->soc->groups[group].grp.name; in intel_get_group_name()
301 *pins = pctrl->soc->groups[group].grp.pins; in intel_get_group_pins()
302 *npins = pctrl->soc->groups[group].grp.npins; in intel_get_group_pins()
313 int locked; in intel_pin_dbg_show() local
337 locked = intel_pad_locked(pctrl, pin); in intel_pin_dbg_show()
340 if (locked || acpi) { in intel_pin_dbg_show()
342 if (locked) in intel_pin_dbg_show()
343 seq_puts(s, "LOCKED"); in intel_pin_dbg_show()
344 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) in intel_pin_dbg_show()
346 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) in intel_pin_dbg_show()
349 if (locked && acpi) in intel_pin_dbg_show()
369 return pctrl->soc->nfunctions; in intel_get_functions_count()
377 return pctrl->soc->functions[function].func.name; in intel_get_function_name()
386 *groups = pctrl->soc->functions[function].func.groups; in intel_get_function_groups()
387 *ngroups = pctrl->soc->functions[function].func.ngroups; in intel_get_function_groups()
396 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; in intel_pinmux_set_mux()
399 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_pinmux_set_mux()
403 * before we can enable the mux for this group. in intel_pinmux_set_mux()
405 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
406 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) in intel_pinmux_set_mux()
407 return -EBUSY; in intel_pinmux_set_mux()
410 /* Now enable the mux setting for each pin in the group */ in intel_pinmux_set_mux()
411 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
415 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); in intel_pinmux_set_mux()
420 if (grp->modes) in intel_pinmux_set_mux()
421 pmode = grp->modes[i]; in intel_pinmux_set_mux()
423 pmode = grp->mode; in intel_pinmux_set_mux()
487 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_request_enable()
490 return -EBUSY; in intel_gpio_request_enable()
518 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_set_direction()
542 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_config_get_pull()
550 return -EINVAL; in intel_config_get_pull()
555 return -EINVAL; in intel_config_get_pull()
581 return -EINVAL; in intel_config_get_pull()
585 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
586 return -EINVAL; in intel_config_get_pull()
590 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
591 return -EINVAL; in intel_config_get_pull()
609 return -EINVAL; in intel_config_get_pull()
624 return -ENOTSUPP; in intel_config_get_debounce()
626 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_config_get_debounce()
630 return -EINVAL; in intel_config_get_debounce()
647 return -ENOTSUPP; in intel_config_get()
665 return -ENOTSUPP; in intel_config_get()
703 return -EINVAL; in intel_config_set_pull()
724 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_set_pull()
725 return -EINVAL; in intel_config_set_pull()
729 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_set_pull()
730 return -EINVAL; in intel_config_set_pull()
734 return -EINVAL; in intel_config_set_pull()
741 return -EINVAL; in intel_config_set_pull()
746 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_config_set_pull()
764 return -ENOTSUPP; in intel_config_set_debounce()
768 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_config_set_debounce()
782 return -EINVAL; in intel_config_set_debounce()
803 return -ENOTSUPP; in intel_config_set()
823 return -ENOTSUPP; in intel_config_set()
844 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
863 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_to_pin()
864 const struct intel_community *comm = &pctrl->communities[i]; in intel_gpio_to_pin()
867 for (j = 0; j < comm->ngpps; j++) { in intel_gpio_to_pin()
868 const struct intel_padgroup *pgrp = &comm->gpps[j]; in intel_gpio_to_pin()
870 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_to_pin()
873 if (offset >= pgrp->gpio_base && in intel_gpio_to_pin()
874 offset < pgrp->gpio_base + pgrp->size) { in intel_gpio_to_pin()
877 pin = pgrp->base + offset - pgrp->gpio_base; in intel_gpio_to_pin()
888 return -EINVAL; in intel_gpio_to_pin()
892 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
907 return -EINVAL; in intel_pin_to_gpio()
911 return -EINVAL; in intel_pin_to_gpio()
913 return pin - padgrp->base + padgrp->gpio_base; in intel_pin_to_gpio()
925 return -EINVAL; in intel_gpio_get()
929 return -EINVAL; in intel_gpio_get()
954 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_set()
973 return -EINVAL; in intel_gpio_get_direction()
977 return -EINVAL; in intel_gpio_get_direction()
979 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_gpio_get_direction()
983 return -EINVAL; in intel_gpio_get_direction()
1028 gpp = padgrp->reg_num; in intel_gpio_irq_ack()
1031 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_ack()
1033 guard(raw_spinlock)(&pctrl->lock); in intel_gpio_irq_ack()
1052 gpp = padgrp->reg_num; in intel_gpio_irq_mask_unmask()
1055 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1056 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1058 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_irq_mask_unmask()
1100 return -EINVAL; in intel_gpio_irq_type()
1108 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); in intel_gpio_irq_type()
1109 return -EPERM; in intel_gpio_irq_type()
1129 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_irq_type()
1155 enable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1157 disable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1159 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); in intel_gpio_irq_wake()
1164 .name = "intel-gpio",
1177 struct gpio_chip *gc = &pctrl->chip; in intel_gpio_community_irq_handler()
1181 for (gpp = 0; gpp < community->ngpps; gpp++) { in intel_gpio_community_irq_handler()
1182 const struct intel_padgroup *padgrp = &community->gpps[gpp]; in intel_gpio_community_irq_handler()
1187 gpp = padgrp->reg_num; in intel_gpio_community_irq_handler()
1189 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_community_irq_handler()
1190 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_community_irq_handler()
1192 scoped_guard(raw_spinlock, &pctrl->lock) { in intel_gpio_community_irq_handler()
1200 for_each_set_bit(gpp_offset, &pending, padgrp->size) in intel_gpio_community_irq_handler()
1201 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); in intel_gpio_community_irq_handler()
1217 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_irq()
1218 community = &pctrl->communities[i]; in intel_gpio_irq()
1229 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_irq_init()
1234 community = &pctrl->communities[i]; in intel_gpio_irq_init()
1236 for (gpp = 0; gpp < community->ngpps; gpp++) { in intel_gpio_irq_init()
1237 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq_init()
1238 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_init()
1265 for (i = 0; i < community->ngpps; i++) { in intel_gpio_add_community_ranges()
1266 const struct intel_padgroup *gpp = &community->gpps[i]; in intel_gpio_add_community_ranges()
1268 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_add_community_ranges()
1271 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in intel_gpio_add_community_ranges()
1272 gpp->gpio_base, gpp->base, in intel_gpio_add_community_ranges()
1273 gpp->size); in intel_gpio_add_community_ranges()
1286 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_add_pin_ranges()
1287 struct intel_community *community = &pctrl->communities[i]; in intel_gpio_add_pin_ranges()
1291 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); in intel_gpio_add_pin_ranges()
1305 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_ngpio()
1306 community = &pctrl->communities[i]; in intel_gpio_ngpio()
1307 for (j = 0; j < community->ngpps; j++) { in intel_gpio_ngpio()
1308 const struct intel_padgroup *gpp = &community->gpps[j]; in intel_gpio_ngpio()
1310 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_ngpio()
1313 if (gpp->gpio_base + gpp->size > ngpio) in intel_gpio_ngpio()
1314 ngpio = gpp->gpio_base + gpp->size; in intel_gpio_ngpio()
1326 pctrl->chip = intel_gpio_chip; in intel_gpio_probe()
1329 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); in intel_gpio_probe()
1330 pctrl->chip.label = dev_name(pctrl->dev); in intel_gpio_probe()
1331 pctrl->chip.parent = pctrl->dev; in intel_gpio_probe()
1332 pctrl->chip.base = -1; in intel_gpio_probe()
1333 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; in intel_gpio_probe()
1334 pctrl->irq = irq; in intel_gpio_probe()
1340 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, in intel_gpio_probe()
1342 dev_name(pctrl->dev), pctrl); in intel_gpio_probe()
1344 dev_err(pctrl->dev, "failed to request interrupt\n"); in intel_gpio_probe()
1349 girq = &pctrl->chip.irq; in intel_gpio_probe()
1352 girq->parent_handler = NULL; in intel_gpio_probe()
1353 girq->num_parents = 0; in intel_gpio_probe()
1354 girq->default_type = IRQ_TYPE_NONE; in intel_gpio_probe()
1355 girq->handler = handle_bad_irq; in intel_gpio_probe()
1356 girq->init_hw = intel_gpio_irq_init_hw; in intel_gpio_probe()
1358 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); in intel_gpio_probe()
1360 dev_err(pctrl->dev, "failed to register gpiochip\n"); in intel_gpio_probe()
1372 size_t i, ngpps = community->ngpps; in intel_pinctrl_add_padgroups_by_gpps()
1374 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_gpps()
1376 return -ENOMEM; in intel_pinctrl_add_padgroups_by_gpps()
1379 gpps[i] = community->gpps[i]; in intel_pinctrl_add_padgroups_by_gpps()
1382 return -EINVAL; in intel_pinctrl_add_padgroups_by_gpps()
1402 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_gpps()
1411 unsigned int npins = community->npins; in intel_pinctrl_add_padgroups_by_size()
1413 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); in intel_pinctrl_add_padgroups_by_size()
1415 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) in intel_pinctrl_add_padgroups_by_size()
1416 return -EINVAL; in intel_pinctrl_add_padgroups_by_size()
1418 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_size()
1420 return -ENOMEM; in intel_pinctrl_add_padgroups_by_size()
1423 unsigned int gpp_size = community->gpp_size; in intel_pinctrl_add_padgroups_by_size()
1426 gpps[i].base = community->pin_base + i * gpp_size; in intel_pinctrl_add_padgroups_by_size()
1428 npins -= gpps[i].size; in intel_pinctrl_add_padgroups_by_size()
1433 padown_num += community->gpp_num_padown_regs; in intel_pinctrl_add_padgroups_by_size()
1436 community->ngpps = ngpps; in intel_pinctrl_add_padgroups_by_size()
1437 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_size()
1445 const struct intel_pinctrl_soc_data *soc = pctrl->soc; in intel_pinctrl_pm_init()
1450 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); in intel_pinctrl_pm_init()
1452 return -ENOMEM; in intel_pinctrl_pm_init()
1454 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, in intel_pinctrl_pm_init()
1457 return -ENOMEM; in intel_pinctrl_pm_init()
1460 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_pm_init()
1461 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_pm_init()
1464 intmask = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1467 return -ENOMEM; in intel_pinctrl_pm_init()
1471 hostown = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1474 return -ENOMEM; in intel_pinctrl_pm_init()
1479 pctrl->context.pads = pads; in intel_pinctrl_pm_init()
1480 pctrl->context.communities = communities; in intel_pinctrl_pm_init()
1497 if (!(community->features & PINCTRL_FEATURE_PWM)) in intel_pinctrl_probe_pwm()
1503 pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); in intel_pinctrl_probe_pwm()
1510 struct device *dev = &pdev->dev; in intel_pinctrl_probe()
1516 return -ENOMEM; in intel_pinctrl_probe()
1518 pctrl->dev = dev; in intel_pinctrl_probe()
1519 pctrl->soc = soc_data; in intel_pinctrl_probe()
1520 raw_spin_lock_init(&pctrl->lock); in intel_pinctrl_probe()
1526 pctrl->ncommunities = pctrl->soc->ncommunities; in intel_pinctrl_probe()
1527 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, in intel_pinctrl_probe()
1528 sizeof(*pctrl->communities), GFP_KERNEL); in intel_pinctrl_probe()
1529 if (!pctrl->communities) in intel_pinctrl_probe()
1530 return -ENOMEM; in intel_pinctrl_probe()
1532 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_probe()
1533 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_probe()
1538 *community = pctrl->soc->communities[i]; in intel_pinctrl_probe()
1540 regs = devm_platform_ioremap_resource(pdev, community->barno); in intel_pinctrl_probe()
1550 return -ENODEV; in intel_pinctrl_probe()
1552 community->features |= PINCTRL_FEATURE_DEBOUNCE; in intel_pinctrl_probe()
1553 community->features |= PINCTRL_FEATURE_1K_PD; in intel_pinctrl_probe()
1562 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; in intel_pinctrl_probe()
1565 community->features |= PINCTRL_FEATURE_PWM; in intel_pinctrl_probe()
1568 community->features |= PINCTRL_FEATURE_BLINK; in intel_pinctrl_probe()
1571 community->features |= PINCTRL_FEATURE_EXP; in intel_pinctrl_probe()
1579 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); in intel_pinctrl_probe()
1584 community->regs = regs; in intel_pinctrl_probe()
1585 community->pad_regs = regs + offset; in intel_pinctrl_probe()
1587 if (community->gpps) in intel_pinctrl_probe()
1607 pctrl->pctldesc = intel_pinctrl_desc; in intel_pinctrl_probe()
1608 pctrl->pctldesc.name = dev_name(dev); in intel_pinctrl_probe()
1609 pctrl->pctldesc.pins = pctrl->soc->pins; in intel_pinctrl_probe()
1610 pctrl->pctldesc.npins = pctrl->soc->npins; in intel_pinctrl_probe()
1612 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); in intel_pinctrl_probe()
1613 if (IS_ERR(pctrl->pctldev)) { in intel_pinctrl_probe()
1615 return PTR_ERR(pctrl->pctldev); in intel_pinctrl_probe()
1632 data = device_get_match_data(&pdev->dev); in intel_pinctrl_probe_by_hid()
1634 return -ENODATA; in intel_pinctrl_probe_by_hid()
1656 struct device *dev = &pdev->dev; in intel_pinctrl_get_soc_data()
1664 if (acpi_dev_uid_match(adev, table[i]->uid)) in intel_pinctrl_get_soc_data()
1673 return ERR_PTR(-ENODEV); in intel_pinctrl_get_soc_data()
1675 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; in intel_pinctrl_get_soc_data()
1676 data = table[pdev->id]; in intel_pinctrl_get_soc_data()
1679 return data ?: ERR_PTR(-ENODATA); in intel_pinctrl_get_soc_data()
1691 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); in intel_pinctrl_should_save()
1700 * BIOS during resume and those are not always locked down so leave in intel_pinctrl_should_save()
1703 if (pd->mux_owner || pd->gpio_owner || in intel_pinctrl_should_save()
1704 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) in intel_pinctrl_should_save()
1735 pads = pctrl->context.pads; in intel_pinctrl_suspend_noirq()
1736 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_suspend_noirq()
1737 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_suspend_noirq()
1741 if (!intel_pinctrl_should_save(pctrl, desc->number)) in intel_pinctrl_suspend_noirq()
1744 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); in intel_pinctrl_suspend_noirq()
1746 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); in intel_pinctrl_suspend_noirq()
1749 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); in intel_pinctrl_suspend_noirq()
1754 communities = pctrl->context.communities; in intel_pinctrl_suspend_noirq()
1755 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_suspend_noirq()
1756 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_suspend_noirq()
1760 base = community->regs + community->ie_offset; in intel_pinctrl_suspend_noirq()
1761 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1764 base = community->regs + community->hostown_offset; in intel_pinctrl_suspend_noirq()
1765 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1789 const struct intel_community *community = &pctrl->communities[c]; in intel_restore_hostown()
1790 const struct intel_padgroup *padgrp = &community->gpps[gpp]; in intel_restore_hostown()
1791 struct device *dev = pctrl->dev; in intel_restore_hostown()
1796 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_restore_hostown()
1799 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) in intel_restore_hostown()
1811 struct device *dev = pctrl->dev; in intel_restore_intmask()
1824 struct device *dev = pctrl->dev; in intel_restore_padcfg()
1847 pads = pctrl->context.pads; in intel_pinctrl_resume_noirq()
1848 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_resume_noirq()
1849 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_resume_noirq()
1851 if (!(intel_pinctrl_should_save(pctrl, desc->number) || in intel_pinctrl_resume_noirq()
1859 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); in intel_pinctrl_resume_noirq()
1860 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); in intel_pinctrl_resume_noirq()
1861 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); in intel_pinctrl_resume_noirq()
1864 communities = pctrl->context.communities; in intel_pinctrl_resume_noirq()
1865 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_resume_noirq()
1866 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_resume_noirq()
1870 base = community->regs + community->ie_offset; in intel_pinctrl_resume_noirq()
1871 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()
1874 base = community->regs + community->hostown_offset; in intel_pinctrl_resume_noirq()
1875 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()