Lines Matching +full:trig +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013, Intel Corporation
28 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
565 offset -= comm->pin_base; in byt_gpio_reg()
574 reg_offset = comm->pad_map[offset] * 16; in byt_gpio_reg()
578 return comm->pad_regs + reg_offset + reg; in byt_gpio_reg()
601 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_simple_mux()
627 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_mixed_mux()
643 const struct intel_function func = vg->soc->functions[func_selector]; in byt_set_mux()
644 const struct intel_pingroup group = vg->soc->groups[group_selector]; in byt_set_mux()
658 /* SCORE pin 92-93 */ in byt_get_gpio_mux()
659 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && in byt_get_gpio_mux()
663 /* SUS pin 11-21 */ in byt_get_gpio_mux()
664 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && in byt_get_gpio_mux()
680 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ in byt_gpio_clear_triggering()
715 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); in byt_gpio_request_enable()
741 dev_info_once(vg->dev, in byt_gpio_direct_irq_check()
816 return -EINVAL; in byt_set_pull_strength()
837 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); in byt_gpio_force_input_mode()
861 return -EINVAL; in byt_pin_config_get()
866 return -EINVAL; in byt_pin_config_get()
874 return -EINVAL; in byt_pin_config_get()
881 return -EINVAL; in byt_pin_config_get()
909 return -EINVAL; in byt_pin_config_get()
914 return -ENOTSUPP; in byt_pin_config_get()
994 return -EINVAL; in byt_pin_config_set()
1009 return -ENOTSUPP; in byt_pin_config_set()
1070 return -EINVAL; in byt_gpio_get_direction()
1080 return -EINVAL; in byt_gpio_get_direction()
1134 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_dbg_show()
1141 pin = vg->soc->pins[i].number; in byt_gpio_dbg_show()
1195 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", in byt_gpio_dbg_show()
1201 comm->pad_map[i], comm->pad_map[i] * 16, in byt_gpio_dbg_show()
1208 seq_printf(s, " %-4s %-3s", pull, pull_str); in byt_gpio_dbg_show()
1213 seq_puts(s, " open-drain"); in byt_gpio_dbg_show()
1306 return -EINVAL; in byt_irq_type()
1335 .name = "BYT-GPIO",
1354 for (base = 0; base < vg->chip.ngpio; base += 32) { in byt_gpio_irq_handler()
1358 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_handler()
1365 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); in byt_gpio_irq_handler()
1367 chip->irq_eoi(data); in byt_gpio_irq_handler()
1374 u32 trig; in byt_direct_irq_sanity_check() local
1376 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, in byt_direct_irq_sanity_check()
1380 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); in byt_direct_irq_sanity_check()
1384 direct_irq = match - direct_irq_mux; in byt_direct_irq_sanity_check()
1385 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ in byt_direct_irq_sanity_check()
1386 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; in byt_direct_irq_sanity_check()
1387 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, in byt_direct_irq_sanity_check()
1392 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ in byt_direct_irq_sanity_check()
1394 * 0x800, to one of the IO-APIC pins according to the mux registers. in byt_direct_irq_sanity_check()
1399 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, in byt_direct_irq_sanity_check()
1400 * selecting edge mode operation then on the first edge the IO-APIC pin goes in byt_direct_irq_sanity_check()
1401 * high, but since no write-to-clear write will be done to the IRQ status reg in byt_direct_irq_sanity_check()
1404 trig = conf0 & BYT_TRIG_MASK; in byt_direct_irq_sanity_check()
1405 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && in byt_direct_irq_sanity_check()
1406 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { in byt_direct_irq_sanity_check()
1407 dev_warn(vg->dev, in byt_direct_irq_sanity_check()
1426 * Clear interrupt triggers for all pins that are GPIOs and in byt_init_irq_valid_mask()
1430 for (i = 0; i < vg->soc->npins; i++) { in byt_init_irq_valid_mask()
1431 unsigned int pin = vg->soc->pins[i].number; in byt_init_irq_valid_mask()
1435 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); in byt_init_irq_valid_mask()
1450 dev_dbg(vg->dev, "disabling GPIO %d\n", i); in byt_init_irq_valid_mask()
1462 for (base = 0; base < vg->soc->npins; base += 32) { in byt_gpio_irq_init_hw()
1466 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_init_hw()
1475 dev_err(vg->dev, in byt_gpio_irq_init_hw()
1486 struct device *dev = vg->dev; in byt_gpio_add_pin_ranges()
1489 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); in byt_gpio_add_pin_ranges()
1498 struct platform_device *pdev = to_platform_device(vg->dev); in byt_gpio_probe()
1503 vg->chip = byt_gpio_chip; in byt_gpio_probe()
1504 gc = &vg->chip; in byt_gpio_probe()
1505 gc->label = dev_name(vg->dev); in byt_gpio_probe()
1506 gc->base = -1; in byt_gpio_probe()
1507 gc->can_sleep = false; in byt_gpio_probe()
1508 gc->add_pin_ranges = byt_gpio_add_pin_ranges; in byt_gpio_probe()
1509 gc->parent = vg->dev; in byt_gpio_probe()
1510 gc->ngpio = vg->soc->npins; in byt_gpio_probe()
1513 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), in byt_gpio_probe()
1515 if (!vg->context.pads) in byt_gpio_probe()
1516 return -ENOMEM; in byt_gpio_probe()
1524 girq = &gc->irq; in byt_gpio_probe()
1526 girq->init_hw = byt_gpio_irq_init_hw; in byt_gpio_probe()
1527 girq->init_valid_mask = byt_init_irq_valid_mask; in byt_gpio_probe()
1528 girq->parent_handler = byt_gpio_irq_handler; in byt_gpio_probe()
1529 girq->num_parents = 1; in byt_gpio_probe()
1530 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, in byt_gpio_probe()
1531 sizeof(*girq->parents), GFP_KERNEL); in byt_gpio_probe()
1532 if (!girq->parents) in byt_gpio_probe()
1533 return -ENOMEM; in byt_gpio_probe()
1534 girq->parents[0] = irq; in byt_gpio_probe()
1535 girq->default_type = IRQ_TYPE_NONE; in byt_gpio_probe()
1536 girq->handler = handle_bad_irq; in byt_gpio_probe()
1539 ret = devm_gpiochip_add_data(vg->dev, gc, vg); in byt_gpio_probe()
1541 dev_err(vg->dev, "failed adding byt-gpio chip\n"); in byt_gpio_probe()
1551 struct platform_device *pdev = to_platform_device(vg->dev); in byt_set_soc_data()
1554 vg->soc = soc; in byt_set_soc_data()
1556 vg->ncommunities = vg->soc->ncommunities; in byt_set_soc_data()
1557 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, in byt_set_soc_data()
1558 sizeof(*vg->communities), GFP_KERNEL); in byt_set_soc_data()
1559 if (!vg->communities) in byt_set_soc_data()
1560 return -ENOMEM; in byt_set_soc_data()
1562 for (i = 0; i < vg->soc->ncommunities; i++) { in byt_set_soc_data()
1563 struct intel_community *comm = vg->communities + i; in byt_set_soc_data()
1565 *comm = vg->soc->communities[i]; in byt_set_soc_data()
1567 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); in byt_set_soc_data()
1568 if (IS_ERR(comm->pad_regs)) in byt_set_soc_data()
1569 return PTR_ERR(comm->pad_regs); in byt_set_soc_data()
1584 struct device *dev = &pdev->dev; in byt_pinctrl_probe()
1594 return -ENOMEM; in byt_pinctrl_probe()
1596 vg->dev = dev; in byt_pinctrl_probe()
1603 vg->pctldesc = byt_pinctrl_desc; in byt_pinctrl_probe()
1604 vg->pctldesc.name = dev_name(dev); in byt_pinctrl_probe()
1605 vg->pctldesc.pins = vg->soc->pins; in byt_pinctrl_probe()
1606 vg->pctldesc.npins = vg->soc->npins; in byt_pinctrl_probe()
1608 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); in byt_pinctrl_probe()
1609 if (IS_ERR(vg->pctldev)) { in byt_pinctrl_probe()
1611 return PTR_ERR(vg->pctldev); in byt_pinctrl_probe()
1630 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_suspend()
1633 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_suspend()
1637 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_suspend()
1641 vg->context.pads[i].conf0 = value; in byt_gpio_suspend()
1645 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_suspend()
1649 vg->context.pads[i].val = value; in byt_gpio_suspend()
1662 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_resume()
1665 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_resume()
1669 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_resume()
1674 vg->context.pads[i].conf0) { in byt_gpio_resume()
1676 value |= vg->context.pads[i].conf0; in byt_gpio_resume()
1683 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_resume()
1688 vg->context.pads[i].val) { in byt_gpio_resume()
1692 v |= vg->context.pads[i].val; in byt_gpio_resume()