Lines Matching +full:phy +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
49 /* mode: RC, EP */
50 int mode; member
56 struct phy *phy; member
67 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
69 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
71 /* Actually We don't care EP/RC mode, but just record it */ in rockchip_p3phy_set_mode()
74 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
77 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
80 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
81 return -EINVAL; in rockchip_p3phy_set_mode()
89 struct phy *phy = priv->phy; in rockchip_p3phy_rk3568_init() local
94 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3568_init()
95 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); in rockchip_p3phy_rk3568_init()
97 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3568_init()
98 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); in rockchip_p3phy_rk3568_init()
99 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3568_init()
105 dev_info(&phy->dev, "bifurcation enabled\n"); in rockchip_p3phy_rk3568_init()
106 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
108 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, in rockchip_p3phy_rk3568_init()
111 dev_dbg(&phy->dev, "bifurcation disabled\n"); in rockchip_p3phy_rk3568_init()
112 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
116 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3568_init()
118 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3568_init()
123 dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3568_init()
135 u8 mode = 0; in rockchip_p3phy_rk3588_init() local
138 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3588_init()
139 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); in rockchip_p3phy_rk3588_init()
142 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3588_init()
143 if (!priv->lanes[i]) in rockchip_p3phy_rk3588_init()
144 mode |= (BIT(i) << 3); in rockchip_p3phy_rk3588_init()
146 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3588_init()
147 mode |= (BIT(i) >> 1); in rockchip_p3phy_rk3588_init()
150 if (!mode) in rockchip_p3phy_rk3588_init()
153 if (mode & (BIT(0) | BIT(1))) in rockchip_p3phy_rk3588_init()
156 if (mode & (BIT(2) | BIT(3))) in rockchip_p3phy_rk3588_init()
160 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); in rockchip_p3phy_rk3588_init()
163 if (!IS_ERR(priv->pipe_grf)) { in rockchip_p3phy_rk3588_init()
164 reg = (mode & (BIT(6) | BIT(7))) >> 6; in rockchip_p3phy_rk3588_init()
166 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, in rockchip_p3phy_rk3588_init()
170 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3588_init()
172 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
176 ret |= regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
181 dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3588_init()
190 static int rochchip_p3phy_init(struct phy *phy) in rochchip_p3phy_init() argument
192 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rochchip_p3phy_init()
195 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rochchip_p3phy_init()
197 dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); in rochchip_p3phy_init()
201 reset_control_assert(priv->p30phy); in rochchip_p3phy_init()
204 if (priv->ops->phy_init) { in rochchip_p3phy_init()
205 ret = priv->ops->phy_init(priv); in rochchip_p3phy_init()
207 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rochchip_p3phy_init()
213 static int rochchip_p3phy_exit(struct phy *phy) in rochchip_p3phy_exit() argument
215 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rochchip_p3phy_exit()
217 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rochchip_p3phy_exit()
218 reset_control_assert(priv->p30phy); in rochchip_p3phy_exit()
232 struct device *dev = &pdev->dev; in rockchip_p3phy_probe()
234 struct device_node *np = dev->of_node; in rockchip_p3phy_probe()
239 return -ENOMEM; in rockchip_p3phy_probe()
241 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in rockchip_p3phy_probe()
242 if (IS_ERR(priv->mmio)) { in rockchip_p3phy_probe()
243 ret = PTR_ERR(priv->mmio); in rockchip_p3phy_probe()
247 priv->ops = of_device_get_match_data(&pdev->dev); in rockchip_p3phy_probe()
248 if (!priv->ops) { in rockchip_p3phy_probe()
250 return -EINVAL; in rockchip_p3phy_probe()
253 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); in rockchip_p3phy_probe()
254 if (IS_ERR(priv->phy_grf)) { in rockchip_p3phy_probe()
256 return PTR_ERR(priv->phy_grf); in rockchip_p3phy_probe()
259 if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) { in rockchip_p3phy_probe()
260 priv->pipe_grf = in rockchip_p3phy_probe()
261 syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_p3phy_probe()
262 "rockchip,pipe-grf"); in rockchip_p3phy_probe()
263 if (IS_ERR(priv->pipe_grf)) in rockchip_p3phy_probe()
266 priv->pipe_grf = NULL; in rockchip_p3phy_probe()
269 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
270 priv->lanes, 2, in rockchip_p3phy_probe()
271 ARRAY_SIZE(priv->lanes)); in rockchip_p3phy_probe()
273 /* if no data-lanes assume aggregation */ in rockchip_p3phy_probe()
274 if (priv->num_lanes == -EINVAL) { in rockchip_p3phy_probe()
275 dev_dbg(dev, "no data-lanes property found\n"); in rockchip_p3phy_probe()
276 priv->num_lanes = 1; in rockchip_p3phy_probe()
277 priv->lanes[0] = 1; in rockchip_p3phy_probe()
278 } else if (priv->num_lanes < 0) { in rockchip_p3phy_probe()
279 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); in rockchip_p3phy_probe()
280 return priv->num_lanes; in rockchip_p3phy_probe()
283 priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); in rockchip_p3phy_probe()
284 if (IS_ERR(priv->phy)) { in rockchip_p3phy_probe()
286 return PTR_ERR(priv->phy); in rockchip_p3phy_probe()
289 priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); in rockchip_p3phy_probe()
290 if (IS_ERR(priv->p30phy)) { in rockchip_p3phy_probe()
291 return dev_err_probe(dev, PTR_ERR(priv->p30phy), in rockchip_p3phy_probe()
292 "failed to get phy reset control\n"); in rockchip_p3phy_probe()
294 if (!priv->p30phy) in rockchip_p3phy_probe()
295 dev_info(dev, "no phy reset control specified\n"); in rockchip_p3phy_probe()
297 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_p3phy_probe()
298 if (priv->num_clks < 1) in rockchip_p3phy_probe()
299 return -ENODEV; in rockchip_p3phy_probe()
302 phy_set_drvdata(priv->phy, priv); in rockchip_p3phy_probe()
308 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
309 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
317 .name = "rockchip-snps-pcie3-phy",
322 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");