Lines Matching +full:no +full:- +full:spread +full:- +full:spectrum
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
153 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
155 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
163 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
164 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
165 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
167 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
172 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
175 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
176 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
178 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
179 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
187 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
191 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
193 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
197 switch (priv->type) { in rockchip_combphy_init()
203 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
204 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
207 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
208 ret = -EINVAL; in rockchip_combphy_init()
213 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
217 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
221 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
224 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
227 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
233 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
242 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
243 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
258 if (args->args_count != 1) { in rockchip_combphy_xlate()
260 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
263 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
265 args->args[0], priv->type); in rockchip_combphy_xlate()
267 priv->type = args->args[0]; in rockchip_combphy_xlate()
269 return priv->phy; in rockchip_combphy_xlate()
276 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
277 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
278 return -EINVAL; in rockchip_combphy_parse_dt()
280 priv->refclk = NULL; in rockchip_combphy_parse_dt()
281 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
282 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
283 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
288 if (!priv->refclk) { in rockchip_combphy_parse_dt()
289 dev_err(dev, "no refclk found\n"); in rockchip_combphy_parse_dt()
290 return -EINVAL; in rockchip_combphy_parse_dt()
293 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
294 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
295 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
296 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
299 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
300 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
301 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
302 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
305 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
307 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
309 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
310 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
311 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
319 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
327 dev_err(dev, "no OF match data provided\n"); in rockchip_combphy_probe()
328 return -EINVAL; in rockchip_combphy_probe()
333 return -ENOMEM; in rockchip_combphy_probe()
335 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
336 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
337 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
341 priv->dev = dev; in rockchip_combphy_probe()
342 priv->type = PHY_NONE; in rockchip_combphy_probe()
343 priv->cfg = phy_cfg; in rockchip_combphy_probe()
349 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
355 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); in rockchip_combphy_probe()
356 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
358 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
362 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
371 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
375 switch (priv->type) { in rk3568_combphy_cfg()
377 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
382 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
383 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
384 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
385 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
389 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
395 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
397 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
405 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
412 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
413 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
415 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
416 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
417 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
418 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
423 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
425 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
432 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
434 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
435 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
436 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
437 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
438 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
442 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
443 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
444 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
445 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
449 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
450 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
451 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
452 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
453 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
457 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
458 return -EINVAL; in rk3568_combphy_cfg()
461 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
465 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
471 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3568_combphy_cfg()
476 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
480 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
481 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
488 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
494 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
495 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
496 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
497 /* downward spread spectrum +500ppm */ in rk3568_combphy_cfg()
505 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
506 return -EINVAL; in rk3568_combphy_cfg()
509 if (priv->ext_refclk) { in rk3568_combphy_cfg()
510 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
511 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
516 val = readl(priv->mmio + PHYREG14); in rk3568_combphy_cfg()
518 writel(val, priv->mmio + PHYREG14); in rk3568_combphy_cfg()
522 if (priv->enable_ssc) { in rk3568_combphy_cfg()
523 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
525 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
532 /* pipe-phy-grf */
559 /* pipe-grf */
571 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
575 switch (priv->type) { in rk3588_combphy_cfg()
577 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
578 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
579 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
580 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
581 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
582 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
585 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
591 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
593 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
601 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
608 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3588_combphy_cfg()
609 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
611 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
612 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
613 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
617 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
619 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
626 writel(val, priv->mmio + PHYREG7); in rk3588_combphy_cfg()
628 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
629 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
630 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
631 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
632 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
633 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
638 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
639 return -EINVAL; in rk3588_combphy_cfg()
642 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
646 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
652 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3588_combphy_cfg()
657 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
660 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
661 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
668 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
671 writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); in rk3588_combphy_cfg()
674 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
675 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
676 /* downward spread spectrum +500ppm */ in rk3588_combphy_cfg()
683 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
684 return -EINVAL; in rk3588_combphy_cfg()
687 if (priv->ext_refclk) { in rk3588_combphy_cfg()
688 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
689 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
694 val = readl(priv->mmio + PHYREG14); in rk3588_combphy_cfg()
696 writel(val, priv->mmio + PHYREG14); in rk3588_combphy_cfg()
700 if (priv->enable_ssc) { in rk3588_combphy_cfg()
701 val = readl(priv->mmio + PHYREG8); in rk3588_combphy_cfg()
703 writel(val, priv->mmio + PHYREG8); in rk3588_combphy_cfg()
710 /* pipe-phy-grf */
731 /* pipe-grf */
745 .compatible = "rockchip,rk3568-naneng-combphy",
749 .compatible = "rockchip,rk3588-naneng-combphy",
759 .name = "rockchip-naneng-combphy",