Lines Matching +full:0 +full:xc8
14 #define QSERDES_QMP_PLL 0x0
15 #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (QSERDES_QMP_PLL + 0x1ac)
16 #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (QSERDES_QMP_PLL + 0x1b0)
17 #define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL (QSERDES_QMP_PLL + 0x1bc)
18 #define QSERDES_COM_CORE_CLK_EN (QSERDES_QMP_PLL + 0x174)
19 #define QSERDES_COM_CORECLK_DIV_MODE0 (QSERDES_QMP_PLL + 0x168)
20 #define QSERDES_COM_CP_CTRL_MODE0 (QSERDES_QMP_PLL + 0x74)
21 #define QSERDES_COM_DEC_START_MODE0 (QSERDES_QMP_PLL + 0xbc)
22 #define QSERDES_COM_DIV_FRAC_START1_MODE0 (QSERDES_QMP_PLL + 0xcc)
23 #define QSERDES_COM_DIV_FRAC_START2_MODE0 (QSERDES_QMP_PLL + 0xd0)
24 #define QSERDES_COM_DIV_FRAC_START3_MODE0 (QSERDES_QMP_PLL + 0xd4)
25 #define QSERDES_COM_HSCLK_HS_SWITCH_SEL (QSERDES_QMP_PLL + 0x15c)
26 #define QSERDES_COM_HSCLK_SEL (QSERDES_QMP_PLL + 0x158)
27 #define QSERDES_COM_LOCK_CMP1_MODE0 (QSERDES_QMP_PLL + 0xac)
28 #define QSERDES_COM_LOCK_CMP2_MODE0 (QSERDES_QMP_PLL + 0xb0)
29 #define QSERDES_COM_PLL_CCTRL_MODE0 (QSERDES_QMP_PLL + 0x84)
30 #define QSERDES_COM_PLL_IVCO (QSERDES_QMP_PLL + 0x58)
31 #define QSERDES_COM_PLL_RCTRL_MODE0 (QSERDES_QMP_PLL + 0x7c)
32 #define QSERDES_COM_SYSCLK_EN_SEL (QSERDES_QMP_PLL + 0x94)
33 #define QSERDES_COM_VCO_TUNE1_MODE0 (QSERDES_QMP_PLL + 0x110)
34 #define QSERDES_COM_VCO_TUNE2_MODE0 (QSERDES_QMP_PLL + 0x114)
35 #define QSERDES_COM_VCO_TUNE_INITVAL2 (QSERDES_QMP_PLL + 0x124)
36 #define QSERDES_COM_C_READY_STATUS (QSERDES_QMP_PLL + 0x178)
37 #define QSERDES_COM_CMN_STATUS (QSERDES_QMP_PLL + 0x140)
39 #define QSERDES_RX 0x600
40 #define QSERDES_RX_UCDR_FO_GAIN (QSERDES_RX + 0x8)
41 #define QSERDES_RX_UCDR_SO_GAIN (QSERDES_RX + 0x14)
42 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (QSERDES_RX + 0x30)
43 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (QSERDES_RX + 0x34)
44 #define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (QSERDES_RX + 0x3c)
45 #define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (QSERDES_RX + 0x40)
46 #define QSERDES_RX_UCDR_PI_CONTROLS (QSERDES_RX + 0x44)
47 #define QSERDES_RX_UCDR_PI_CTRL2 (QSERDES_RX + 0x48)
48 #define QSERDES_RX_RX_TERM_BW (QSERDES_RX + 0x80)
49 #define QSERDES_RX_VGA_CAL_CNTRL2 (QSERDES_RX + 0xd8)
50 #define QSERDES_RX_GM_CAL (QSERDES_RX + 0xdc)
51 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (QSERDES_RX + 0xe8)
52 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (QSERDES_RX + 0xec)
53 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (QSERDES_RX + 0xf0)
54 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (QSERDES_RX + 0xf4)
55 #define QSERDES_RX_RX_IDAC_TSETTLE_LOW (QSERDES_RX + 0xf8)
56 #define QSERDES_RX_RX_IDAC_TSETTLE_HIGH (QSERDES_RX + 0xfc)
57 #define QSERDES_RX_RX_IDAC_MEASURE_TIME (QSERDES_RX + 0x100)
58 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (QSERDES_RX + 0x110)
59 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (QSERDES_RX + 0x114)
60 #define QSERDES_RX_SIGDET_CNTRL (QSERDES_RX + 0x11c)
61 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL (QSERDES_RX + 0x124)
62 #define QSERDES_RX_RX_BAND (QSERDES_RX + 0x128)
63 #define QSERDES_RX_RX_MODE_00_LOW (QSERDES_RX + 0x15c)
64 #define QSERDES_RX_RX_MODE_00_HIGH (QSERDES_RX + 0x160)
65 #define QSERDES_RX_RX_MODE_00_HIGH2 (QSERDES_RX + 0x164)
66 #define QSERDES_RX_RX_MODE_00_HIGH3 (QSERDES_RX + 0x168)
67 #define QSERDES_RX_RX_MODE_00_HIGH4 (QSERDES_RX + 0x16c)
68 #define QSERDES_RX_RX_MODE_01_LOW (QSERDES_RX + 0x170)
69 #define QSERDES_RX_RX_MODE_01_HIGH (QSERDES_RX + 0x174)
70 #define QSERDES_RX_RX_MODE_01_HIGH2 (QSERDES_RX + 0x178)
71 #define QSERDES_RX_RX_MODE_01_HIGH3 (QSERDES_RX + 0x17c)
72 #define QSERDES_RX_RX_MODE_01_HIGH4 (QSERDES_RX + 0x180)
73 #define QSERDES_RX_RX_MODE_10_LOW (QSERDES_RX + 0x184)
74 #define QSERDES_RX_RX_MODE_10_HIGH (QSERDES_RX + 0x188)
75 #define QSERDES_RX_RX_MODE_10_HIGH2 (QSERDES_RX + 0x18c)
76 #define QSERDES_RX_RX_MODE_10_HIGH3 (QSERDES_RX + 0x190)
77 #define QSERDES_RX_RX_MODE_10_HIGH4 (QSERDES_RX + 0x194)
78 #define QSERDES_RX_DCC_CTRL1 (QSERDES_RX + 0x1a8)
80 #define QSERDES_TX 0x400
81 #define QSERDES_TX_TX_BAND (QSERDES_TX + 0x24)
82 #define QSERDES_TX_SLEW_CNTL (QSERDES_TX + 0x28)
83 #define QSERDES_TX_RES_CODE_LANE_OFFSET_TX (QSERDES_TX + 0x3c)
84 #define QSERDES_TX_RES_CODE_LANE_OFFSET_RX (QSERDES_TX + 0x40)
85 #define QSERDES_TX_LANE_MODE_1 (QSERDES_TX + 0x84)
86 #define QSERDES_TX_LANE_MODE_3 (QSERDES_TX + 0x8c)
87 #define QSERDES_TX_RCV_DETECT_LVL_2 (QSERDES_TX + 0xa4)
88 #define QSERDES_TX_TRAN_DRVR_EMP_EN (QSERDES_TX + 0xc0)
90 #define QSERDES_PCS 0xC00
91 #define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0)
92 #define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
93 #define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8)
94 #define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc)
95 #define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
96 #define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
97 #define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8)
98 #define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc)
99 #define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)
100 #define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94)
102 #define QSERDES_COM_C_READY BIT(0)
103 #define QSERDES_PCS_READY BIT(0)
115 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
116 regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
118 regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
119 regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
120 regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_1g()
121 regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_1g()
122 regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
123 regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
124 regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
125 regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x82); in qcom_dwmac_sgmii_phy_init_1g()
126 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55); in qcom_dwmac_sgmii_phy_init_1g()
127 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55); in qcom_dwmac_sgmii_phy_init_1g()
128 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03); in qcom_dwmac_sgmii_phy_init_1g()
129 regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0x24); in qcom_dwmac_sgmii_phy_init_1g()
131 regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02); in qcom_dwmac_sgmii_phy_init_1g()
132 regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
133 regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
134 regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
135 regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
136 regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
137 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9); in qcom_dwmac_sgmii_phy_init_1g()
138 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E); in qcom_dwmac_sgmii_phy_init_1g()
139 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); in qcom_dwmac_sgmii_phy_init_1g()
141 regmap_write(regmap, QSERDES_TX_TX_BAND, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
142 regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
143 regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
144 regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
145 regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
146 regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
147 regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12); in qcom_dwmac_sgmii_phy_init_1g()
148 regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
150 regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
151 regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
152 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
153 regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); in qcom_dwmac_sgmii_phy_init_1g()
154 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
155 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
156 regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81); in qcom_dwmac_sgmii_phy_init_1g()
157 regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80); in qcom_dwmac_sgmii_phy_init_1g()
158 regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
159 regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_1g()
160 regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
161 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
162 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
163 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); in qcom_dwmac_sgmii_phy_init_1g()
164 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
165 regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80); in qcom_dwmac_sgmii_phy_init_1g()
166 regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
167 regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20); in qcom_dwmac_sgmii_phy_init_1g()
168 regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); in qcom_dwmac_sgmii_phy_init_1g()
169 regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
170 regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
171 regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); in qcom_dwmac_sgmii_phy_init_1g()
172 regmap_write(regmap, QSERDES_RX_RX_BAND, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
173 regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
174 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
175 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
176 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
177 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_1g()
178 regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
179 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
180 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
181 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
182 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_1g()
183 regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
184 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
185 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
186 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B); in qcom_dwmac_sgmii_phy_init_1g()
187 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7); in qcom_dwmac_sgmii_phy_init_1g()
188 regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
190 regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
191 regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); in qcom_dwmac_sgmii_phy_init_1g()
192 regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); in qcom_dwmac_sgmii_phy_init_1g()
193 regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); in qcom_dwmac_sgmii_phy_init_1g()
194 regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_1g()
195 regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
196 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
198 regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
203 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
204 regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
206 regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
207 regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_2p5g()
208 regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_2p5g()
209 regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_2p5g()
210 regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_2p5g()
211 regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_2p5g()
212 regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x41); in qcom_dwmac_sgmii_phy_init_2p5g()
213 regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x7A); in qcom_dwmac_sgmii_phy_init_2p5g()
214 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
215 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x20); in qcom_dwmac_sgmii_phy_init_2p5g()
216 regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
217 regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0xA1); in qcom_dwmac_sgmii_phy_init_2p5g()
219 regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02); in qcom_dwmac_sgmii_phy_init_2p5g()
220 regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
221 regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x03); in qcom_dwmac_sgmii_phy_init_2p5g()
222 regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
223 regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x05); in qcom_dwmac_sgmii_phy_init_2p5g()
224 regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
225 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD); in qcom_dwmac_sgmii_phy_init_2p5g()
226 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C); in qcom_dwmac_sgmii_phy_init_2p5g()
227 regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); in qcom_dwmac_sgmii_phy_init_2p5g()
229 regmap_write(regmap, QSERDES_TX_TX_BAND, 0x04); in qcom_dwmac_sgmii_phy_init_2p5g()
230 regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
231 regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09); in qcom_dwmac_sgmii_phy_init_2p5g()
232 regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x02); in qcom_dwmac_sgmii_phy_init_2p5g()
233 regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05); in qcom_dwmac_sgmii_phy_init_2p5g()
234 regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
235 regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12); in qcom_dwmac_sgmii_phy_init_2p5g()
236 regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
238 regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
239 regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06); in qcom_dwmac_sgmii_phy_init_2p5g()
240 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
241 regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); in qcom_dwmac_sgmii_phy_init_2p5g()
242 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
243 regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
244 regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81); in qcom_dwmac_sgmii_phy_init_2p5g()
245 regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80); in qcom_dwmac_sgmii_phy_init_2p5g()
246 regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
247 regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_2p5g()
248 regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
249 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); in qcom_dwmac_sgmii_phy_init_2p5g()
250 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
251 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); in qcom_dwmac_sgmii_phy_init_2p5g()
252 regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
253 regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80); in qcom_dwmac_sgmii_phy_init_2p5g()
254 regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
255 regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20); in qcom_dwmac_sgmii_phy_init_2p5g()
256 regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); in qcom_dwmac_sgmii_phy_init_2p5g()
257 regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
258 regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
259 regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); in qcom_dwmac_sgmii_phy_init_2p5g()
260 regmap_write(regmap, QSERDES_RX_RX_BAND, 0x18); in qcom_dwmac_sgmii_phy_init_2p5g()
261 regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0x18); in qcom_dwmac_sgmii_phy_init_2p5g()
262 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
263 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
264 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
265 regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB8); in qcom_dwmac_sgmii_phy_init_2p5g()
266 regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_2p5g()
267 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
268 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
269 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_2p5g()
270 regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_2p5g()
271 regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_2p5g()
272 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
273 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
274 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B); in qcom_dwmac_sgmii_phy_init_2p5g()
275 regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7); in qcom_dwmac_sgmii_phy_init_2p5g()
276 regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
278 regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
279 regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); in qcom_dwmac_sgmii_phy_init_2p5g()
280 regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); in qcom_dwmac_sgmii_phy_init_2p5g()
281 regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); in qcom_dwmac_sgmii_phy_init_2p5g()
282 regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_2p5g()
283 regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C); in qcom_dwmac_sgmii_phy_init_2p5g()
284 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
286 regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
343 return 0; in qcom_dwmac_sgmii_phy_calibrate()
357 regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_power_off()
358 regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_power_off()
360 regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_power_off()
361 regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_power_off()
365 return 0; in qcom_dwmac_sgmii_phy_power_off()
408 base = devm_platform_ioremap_resource(pdev, 0); in qcom_dwmac_sgmii_phy_probe()
431 return 0; in qcom_dwmac_sgmii_phy_probe()