Lines Matching full:qmp
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
32 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
33 #include "phy-qcom-qmp-pcie-qhp.h"
2272 /* QMP PHY pipe clock interface rate */
3212 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) in qmp_pcie_init_port_b() argument
3214 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
3218 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
3219 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
3220 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
3221 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
3230 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) in qmp_pcie_init_registers() argument
3232 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
3233 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
3234 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers()
3235 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
3236 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
3237 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
3238 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers()
3239 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
3240 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
3258 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
3260 qmp_pcie_init_port_b(qmp, tbls); in qmp_pcie_init_registers()
3268 struct qmp_pcie *qmp = phy_get_drvdata(phy); in qmp_pcie_init() local
3269 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
3272 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3274 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
3278 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3280 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
3284 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
3286 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
3292 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3294 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
3298 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
3305 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3307 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3314 struct qmp_pcie *qmp = phy_get_drvdata(phy); in qmp_pcie_exit() local
3315 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
3317 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
3319 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
3321 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
3328 struct qmp_pcie *qmp = phy_get_drvdata(phy); in qmp_pcie_power_on() local
3329 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
3331 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on()
3339 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
3344 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
3345 qmp_pcie_init_registers(qmp, mode_tbls); in qmp_pcie_power_on()
3347 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3351 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
3353 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
3371 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
3378 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3385 struct qmp_pcie *qmp = phy_get_drvdata(phy); in qmp_pcie_power_off() local
3386 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
3388 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
3391 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
3394 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
3398 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
3432 struct qmp_pcie *qmp = phy_get_drvdata(phy); in qmp_pcie_set_mode() local
3437 qmp->mode = submode; in qmp_pcie_set_mode()
3454 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) in qmp_pcie_vreg_init() argument
3456 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
3457 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
3461 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
3462 if (!qmp->vregs) in qmp_pcie_vreg_init()
3466 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
3468 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
3471 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) in qmp_pcie_reset_init() argument
3473 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
3474 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
3478 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
3479 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
3480 if (!qmp->resets) in qmp_pcie_reset_init()
3484 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
3486 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
3491 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
3492 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
3493 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
3500 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) in qmp_pcie_clk_init() argument
3502 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
3506 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
3507 if (!qmp->clks) in qmp_pcie_clk_init()
3511 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
3513 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
3539 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) in phy_pipe_clk_register() argument
3541 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
3547 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
3554 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
3557 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
3558 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
3564 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
3576 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in phy_pipe_clk_register()
3579 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) in qmp_pcie_parse_dt_legacy() argument
3581 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
3582 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
3583 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
3586 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
3587 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
3588 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
3596 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
3597 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
3598 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
3601 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
3603 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
3604 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
3605 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
3607 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
3608 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
3609 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
3612 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
3613 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
3614 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
3616 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
3617 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
3618 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
3620 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
3622 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
3625 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
3626 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
3627 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
3629 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
3633 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
3643 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
3644 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
3645 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
3650 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) in qmp_pcie_get_4ln_config() argument
3656 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
3664 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
3670 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
3674 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
3676 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
3681 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) in qmp_pcie_parse_dt() argument
3683 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
3684 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
3686 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
3693 ret = qmp_pcie_get_4ln_config(qmp); in qmp_pcie_parse_dt()
3701 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
3702 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
3703 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
3704 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
3705 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
3708 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
3709 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
3712 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
3713 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
3714 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
3715 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
3719 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
3721 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
3722 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
3723 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
3725 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
3729 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
3741 struct qmp_pcie *qmp; in qmp_pcie_probe() local
3744 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); in qmp_pcie_probe()
3745 if (!qmp) in qmp_pcie_probe()
3748 qmp->dev = dev; in qmp_pcie_probe()
3750 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
3751 if (!qmp->cfg) in qmp_pcie_probe()
3754 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
3755 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
3757 ret = qmp_pcie_clk_init(qmp); in qmp_pcie_probe()
3761 ret = qmp_pcie_reset_init(qmp); in qmp_pcie_probe()
3765 ret = qmp_pcie_vreg_init(qmp); in qmp_pcie_probe()
3772 ret = qmp_pcie_parse_dt_legacy(qmp, np); in qmp_pcie_probe()
3775 ret = qmp_pcie_parse_dt(qmp); in qmp_pcie_probe()
3780 ret = phy_pipe_clk_register(qmp, np); in qmp_pcie_probe()
3784 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
3786 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
3787 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
3788 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
3793 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
3808 .compatible = "qcom,ipq6018-qmp-pcie-phy",
3811 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
3814 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3817 .compatible = "qcom,msm8998-qmp-pcie-phy",
3820 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
3823 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
3826 .compatible = "qcom,sc8180x-qmp-pcie-phy",
3829 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
3832 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
3835 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
3841 .compatible = "qcom,sdm845-qmp-pcie-phy",
3844 .compatible = "qcom,sdx55-qmp-pcie-phy",
3847 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
3850 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
3853 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
3856 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3859 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
3862 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3865 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3868 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3871 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3874 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3877 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3880 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3883 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
3886 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
3896 .name = "qcom-qmp-pcie-phy",
3904 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");