494 enum cmu_type_t {
499 enum mux_type_t {
504 enum clk_type_t {
510 enum xgene_phy_mode {
534 	enum xgene_phy_mode mode;		/* Mode of operation */
535 	enum clk_type_t clk_type;	/* Input clock selection */
594 static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_wr()
611 static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_rd()
625 static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_toggle1to0()
638 static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_clrbits()
648 static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_setbits()
705 				       enum cmu_type_t cmu_type,  in xgene_phy_cfg_cmu_clk_type()
706 				       enum clk_type_t clk_type)  in xgene_phy_cfg_cmu_clk_type()
759 					enum cmu_type_t cmu_type,  in xgene_phy_sata_cfg_cmu_core()
760 					enum clk_type_t clk_type)  in xgene_phy_sata_cfg_cmu_core()
914 				 enum cmu_type_t cmu_type)  in xgene_phy_ssc_enable()
1136 				 enum cmu_type_t cmu_type,  in xgene_phy_cal_rdy_chk()
1137 				 enum clk_type_t clk_type)  in xgene_phy_cal_rdy_chk()
1236 				     enum cmu_type_t cmu_type,  in xgene_phy_pdwn_force_vco()
1237 				     enum clk_type_t clk_type)  in xgene_phy_pdwn_force_vco()
1254 				  enum clk_type_t clk_type, int ssc_enable)  in xgene_phy_hw_init_sata()
1318 				   enum clk_type_t clk_type,  in xgene_phy_hw_initialize()