Lines Matching +full:ddr +full:- +full:config

1 # SPDX-License-Identifier: GPL-2.0-only
9 config ARM_CCI_PMU
17 	  If compiled as a module, it will be called arm-cci.
19 config ARM_CCI400_PMU
20 	bool "support CCI-400"
25 	  CCI-400 provides 4 independent event counters counting events related
28 config ARM_CCI5xx_PMU
29 	bool "support CCI-500/CCI-550"
33 	  CCI-500/CCI-550 both provide 8 independent event counters, which can
37 config ARM_CCN
44 config ARM_CMN
45 	tristate "Arm CMN-600 PMU support"
48 	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
51 config ARM_PMU
56 	  Say y if you want to use CPU performance monitors on ARM-based
59 config RISCV_PMU
61 	bool "RISC-V PMU framework"
64 	  Say y if you want to use CPU performance monitors on RISCV-based
69 config RISCV_PMU_LEGACY
71 	bool "RISC-V legacy PMU implementation"
75 	  implementation on RISC-V based systems. This only allows counting
79 config RISCV_PMU_SBI
81 	bool "RISC-V PMU based on SBI PMU extension"
85 	  using SBI PMU extension on RISC-V based systems. This option provides
89 config ARM_PMU_ACPI
93 config ARM_SMMU_V3_PMU
103 config ARM_PMUV3
113 config ARM_DSU_PMU
122 config FSL_IMX8_DDR_PMU
123 	tristate "Freescale i.MX8 DDR perf monitor"
126 	  Provides support for the DDR performance monitor in i.MX8, which
130 config FSL_IMX9_DDR_PMU
131 	tristate "Freescale i.MX9 DDR perf monitor"
134 	 Provides support for the DDR performance monitor in i.MX9, which
138 config QCOM_L2_PMU
139 	bool "Qualcomm Technologies L2-cache PMU"
148 config QCOM_L3_PMU
149 	bool "Qualcomm Technologies L3-cache PMU"
158 config THUNDERX2_PMU
168 config XGENE_PMU
170         bool "APM X-Gene SoC PMU"
173           Say y if you want to use APM X-Gene SoC performance monitors.
175 config ARM_SPE_PMU
183 config ARM_DMC620_PMU
184 	tristate "Enable PMU support for the ARM DMC-620 memory controller"
187 	  Support for PMU events monitoring on the ARM DMC-620 memory
190 config MARVELL_CN10K_TAD_PMU
191 	tristate "Marvell CN10K LLC-TAD PMU"
194 	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
197 config APPLE_M1_CPU_PMU
201 	  Provides support for the non-architectural CPU PMUs present on
204 config ALIBABA_UNCORE_DRW_PMU
205 	tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
208 	  Support for Driveway PMU events monitoring on Yitian 710 DDR
209 	  Sub-system.
213 config MARVELL_CN10K_DDR_PMU
217 	  Enable perf support for Marvell DDR Performance monitoring
220 config DWC_PCIE_PMU
231 config CXL_PMU