Lines Matching +full:add +full:- +full:pmem
1 // SPDX-License-Identifier: GPL-2.0
51 if (r->domain_nr == domain_nr) in get_pci_domain_busn_res()
52 return &r->res; in get_pci_domain_busn_res()
58 r->domain_nr = domain_nr; in get_pci_domain_busn_res()
59 r->res.start = 0; in get_pci_domain_busn_res()
60 r->res.end = 0xff; in get_pci_domain_busn_res()
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; in get_pci_domain_busn_res()
63 list_add_tail(&r->list, &pci_domain_busn_res_list); in get_pci_domain_busn_res()
65 return &r->res; in get_pci_domain_busn_res()
92 put_device(pci_bus->bridge); in release_pcibus_dev()
120 size = size & ~(size-1); in pci_size()
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) in pci_size()
153 /* 1M mem BAR treated as 32-bit BAR */ in decode_bar()
159 /* mem unknown type treated as 32-bit BAR */ in decode_bar()
168 * __pci_read_base - Read a PCI BAR
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
183 const char *res_name = pci_resource_name(dev, res - dev->resource); in __pci_read_base()
188 if (!dev->mmio_always_on) { in __pci_read_base()
196 res->name = pci_name(dev); in __pci_read_base()
220 res->flags = decode_bar(dev, l); in __pci_read_base()
221 res->flags |= IORESOURCE_SIZEALIGN; in __pci_read_base()
222 if (res->flags & IORESOURCE_IO) { in __pci_read_base()
233 res->flags |= IORESOURCE_ROM_ENABLE; in __pci_read_base()
239 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
262 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; in __pci_read_base()
266 res->start = 0; in __pci_read_base()
267 res->end = 0; in __pci_read_base()
274 /* Above 32-bit boundary; try to reallocate */ in __pci_read_base()
275 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
276 res->start = 0; in __pci_read_base()
277 res->end = sz64 - 1; in __pci_read_base()
285 region.end = l64 + sz64 - 1; in __pci_read_base()
287 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
302 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
303 res->start = 0; in __pci_read_base()
304 res->end = region.end - region.start; in __pci_read_base()
313 res->flags = 0; in __pci_read_base()
315 if (res->flags) in __pci_read_base()
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; in __pci_read_base()
325 if (dev->non_compliant_bars) in pci_read_bases()
329 if (dev->is_virtfn) in pci_read_bases()
333 struct resource *res = &dev->resource[pos]; in pci_read_bases()
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
340 dev->rom_base_reg = rom; in pci_read_bases()
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | in pci_read_bases()
356 if (dev->io_window_1k) { in pci_read_bridge_io()
377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; in pci_read_bridge_io()
379 region.end = limit + io_granularity - 1; in pci_read_bridge_io()
380 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; in pci_read_bridge_mmio()
401 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | in pci_read_bridge_mmio_pref()
449 if (res->flags & PCI_PREF_RANGE_TYPE_64) in pci_read_bridge_mmio_pref()
450 res->flags |= IORESOURCE_MEM_64; in pci_read_bridge_mmio_pref()
453 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
463 u32 pmem, tmp; in pci_read_bridge_windows() local
471 bridge->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_windows()
480 bridge->io_window = 1; in pci_read_bridge_windows()
491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) in pci_read_bridge_windows()
494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); in pci_read_bridge_windows()
495 if (!pmem) { in pci_read_bridge_windows()
498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); in pci_read_bridge_windows()
501 if (!pmem) in pci_read_bridge_windows()
504 bridge->pref_window = 1; in pci_read_bridge_windows()
506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { in pci_read_bridge_windows()
509 * Bridge claims to have a 64-bit prefetchable memory in pci_read_bridge_windows()
513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); in pci_read_bridge_windows()
517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); in pci_read_bridge_windows()
519 bridge->pref_64_window = 1; in pci_read_bridge_windows()
527 struct pci_dev *dev = child->self; in pci_read_bridge_bases()
535 &child->busn_res, in pci_read_bridge_bases()
536 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
542 pci_read_bridge_io(child->self, child->resource[0], false); in pci_read_bridge_bases()
543 pci_read_bridge_mmio(child->self, child->resource[1], false); in pci_read_bridge_bases()
544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); in pci_read_bridge_bases()
546 if (dev->transparent) { in pci_read_bridge_bases()
547 pci_bus_for_each_resource(child->parent, res) { in pci_read_bridge_bases()
548 if (res && res->flags) { in pci_read_bridge_bases()
566 INIT_LIST_HEAD(&b->node); in pci_alloc_bus()
567 INIT_LIST_HEAD(&b->children); in pci_alloc_bus()
568 INIT_LIST_HEAD(&b->devices); in pci_alloc_bus()
569 INIT_LIST_HEAD(&b->slots); in pci_alloc_bus()
570 INIT_LIST_HEAD(&b->resources); in pci_alloc_bus()
571 b->max_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
572 b->cur_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
575 b->domain_nr = parent->domain_nr; in pci_alloc_bus()
584 if (bridge->release_fn) in pci_release_host_bridge_dev()
585 bridge->release_fn(bridge); in pci_release_host_bridge_dev()
587 pci_free_resource_list(&bridge->windows); in pci_release_host_bridge_dev()
588 pci_free_resource_list(&bridge->dma_ranges); in pci_release_host_bridge_dev()
594 INIT_LIST_HEAD(&bridge->windows); in pci_init_host_bridge()
595 INIT_LIST_HEAD(&bridge->dma_ranges); in pci_init_host_bridge()
603 bridge->native_aer = 1; in pci_init_host_bridge()
604 bridge->native_pcie_hotplug = 1; in pci_init_host_bridge()
605 bridge->native_shpc_hotplug = 1; in pci_init_host_bridge()
606 bridge->native_pme = 1; in pci_init_host_bridge()
607 bridge->native_ltr = 1; in pci_init_host_bridge()
608 bridge->native_dpc = 1; in pci_init_host_bridge()
609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; in pci_init_host_bridge()
610 bridge->native_cxl_error = 1; in pci_init_host_bridge()
612 device_initialize(&bridge->dev); in pci_init_host_bridge()
624 bridge->dev.release = pci_release_host_bridge_dev; in pci_alloc_host_bridge()
645 bridge->dev.parent = dev; in devm_pci_alloc_host_bridge()
662 put_device(&bridge->dev); in pci_free_host_bridge()
713 "66 MHz PCI-X", /* 0x02 */ in pci_speed_string()
714 "100 MHz PCI-X", /* 0x03 */ in pci_speed_string()
715 "133 MHz PCI-X", /* 0x04 */ in pci_speed_string()
720 "66 MHz PCI-X 266", /* 0x09 */ in pci_speed_string()
721 "100 MHz PCI-X 266", /* 0x0a */ in pci_speed_string()
722 "133 MHz PCI-X 266", /* 0x0b */ in pci_speed_string()
728 "66 MHz PCI-X 533", /* 0x11 */ in pci_speed_string()
729 "100 MHz PCI-X 533", /* 0x12 */ in pci_speed_string()
730 "133 MHz PCI-X 533", /* 0x13 */ in pci_speed_string()
747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; in pcie_update_link_speed()
784 struct pci_dev *bridge = bus->self; in pci_set_bus_speed()
794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); in pci_set_bus_speed()
797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); in pci_set_bus_speed()
821 bus->max_bus_speed = max; in pci_set_bus_speed()
822 bus->cur_bus_speed = in pci_set_bus_speed()
833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; in pci_set_bus_speed()
845 d = dev_get_msi_domain(bus->bridge); in pci_host_bridge_msi_domain()
878 * created by an SR-IOV device. Walk up to the first bridge device in pci_set_bus_msi_domain()
881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { in pci_set_bus_msi_domain()
882 if (b->self) in pci_set_bus_msi_domain()
883 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
889 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
894 struct device *parent = bridge->dev.parent; in pci_register_host_bridge()
906 return -ENOMEM; in pci_register_host_bridge()
908 bridge->bus = bus; in pci_register_host_bridge()
910 bus->sysdata = bridge->sysdata; in pci_register_host_bridge()
911 bus->ops = bridge->ops; in pci_register_host_bridge()
912 bus->number = bus->busn_res.start = bridge->busnr; in pci_register_host_bridge()
914 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) in pci_register_host_bridge()
915 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); in pci_register_host_bridge()
917 bus->domain_nr = bridge->domain_nr; in pci_register_host_bridge()
918 if (bus->domain_nr < 0) { in pci_register_host_bridge()
919 err = bus->domain_nr; in pci_register_host_bridge()
924 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); in pci_register_host_bridge()
927 dev_dbg(&b->dev, "bus already known\n"); in pci_register_host_bridge()
928 err = -EEXIST; in pci_register_host_bridge()
932 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), in pci_register_host_bridge()
933 bridge->busnr); in pci_register_host_bridge()
940 list_splice_init(&bridge->windows, &resources); in pci_register_host_bridge()
941 err = device_add(&bridge->dev); in pci_register_host_bridge()
943 put_device(&bridge->dev); in pci_register_host_bridge()
946 bus->bridge = get_device(&bridge->dev); in pci_register_host_bridge()
947 device_enable_async_suspend(bus->bridge); in pci_register_host_bridge()
950 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && in pci_register_host_bridge()
952 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in pci_register_host_bridge()
955 set_dev_node(bus->bridge, pcibus_to_node(bus)); in pci_register_host_bridge()
957 bus->dev.class = &pcibus_class; in pci_register_host_bridge()
958 bus->dev.parent = bus->bridge; in pci_register_host_bridge()
960 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); in pci_register_host_bridge()
961 name = dev_name(&bus->dev); in pci_register_host_bridge()
963 err = device_register(&bus->dev); in pci_register_host_bridge()
969 if (bus->ops->add_bus) { in pci_register_host_bridge()
970 err = bus->ops->add_bus(bus); in pci_register_host_bridge()
972 dev_err(&bus->dev, "failed to add bus: %d\n", err); in pci_register_host_bridge()
984 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); in pci_register_host_bridge()
988 if (list_is_last(&window->node, &resources)) in pci_register_host_bridge()
992 offset = window->offset; in pci_register_host_bridge()
993 res = window->res; in pci_register_host_bridge()
994 next_offset = next->offset; in pci_register_host_bridge()
995 next_res = next->res; in pci_register_host_bridge()
997 if (res->flags != next_res->flags || offset != next_offset) in pci_register_host_bridge()
1000 if (res->end + 1 == next_res->start) { in pci_register_host_bridge()
1001 next_res->start = res->start; in pci_register_host_bridge()
1002 res->flags = res->start = res->end = 0; in pci_register_host_bridge()
1006 /* Add initial resources to the bus */ in pci_register_host_bridge()
1008 offset = window->offset; in pci_register_host_bridge()
1009 res = window->res; in pci_register_host_bridge()
1010 if (!res->flags && !res->start && !res->end) { in pci_register_host_bridge()
1016 list_move_tail(&window->node, &bridge->windows); in pci_register_host_bridge()
1018 if (res->flags & IORESOURCE_BUS) in pci_register_host_bridge()
1019 pci_bus_insert_busn_res(bus, bus->number, res->end); in pci_register_host_bridge()
1025 fmt = " (bus address [%#06llx-%#06llx])"; in pci_register_host_bridge()
1027 fmt = " (bus address [%#010llx-%#010llx])"; in pci_register_host_bridge()
1030 (unsigned long long)(res->start - offset), in pci_register_host_bridge()
1031 (unsigned long long)(res->end - offset)); in pci_register_host_bridge()
1035 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); in pci_register_host_bridge()
1039 list_add_tail(&bus->node, &pci_root_buses); in pci_register_host_bridge()
1045 put_device(&bridge->dev); in pci_register_host_bridge()
1046 device_del(&bridge->dev); in pci_register_host_bridge()
1065 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_bridge_child_ext_cfg_accessible()
1081 * - PCI-to-PCI bridges in pci_bridge_child_ext_cfg_accessible()
1082 * - PCIe-to-PCI/PCI-X forward bridges in pci_bridge_child_ext_cfg_accessible()
1083 * - PCI/PCI-X-to-PCIe reverse bridges in pci_bridge_child_ext_cfg_accessible()
1085 * if the bridge supports PCI-X Mode 2. in pci_bridge_child_ext_cfg_accessible()
1108 child->parent = parent; in pci_alloc_child_bus()
1109 child->sysdata = parent->sysdata; in pci_alloc_child_bus()
1110 child->bus_flags = parent->bus_flags; in pci_alloc_child_bus()
1113 if (host->child_ops) in pci_alloc_child_bus()
1114 child->ops = host->child_ops; in pci_alloc_child_bus()
1116 child->ops = parent->ops; in pci_alloc_child_bus()
1122 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
1123 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
1126 child->number = child->busn_res.start = busnr; in pci_alloc_child_bus()
1127 child->primary = parent->busn_res.start; in pci_alloc_child_bus()
1128 child->busn_res.end = 0xff; in pci_alloc_child_bus()
1131 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
1135 child->self = bridge; in pci_alloc_child_bus()
1136 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
1137 child->dev.parent = child->bridge; in pci_alloc_child_bus()
1147 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; in pci_alloc_child_bus()
1153 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; in pci_alloc_child_bus()
1154 child->resource[i]->name = child->name; in pci_alloc_child_bus()
1156 bridge->subordinate = child; in pci_alloc_child_bus()
1160 ret = device_register(&child->dev); in pci_alloc_child_bus()
1165 if (child->ops->add_bus) { in pci_alloc_child_bus()
1166 ret = child->ops->add_bus(child); in pci_alloc_child_bus()
1168 dev_err(&child->dev, "failed to add bus: %d\n", ret); in pci_alloc_child_bus()
1185 list_add_tail(&child->node, &parent->children); in pci_add_new_bus()
1206 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1222 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) in pci_ea_fixed_busnrs()
1243 * pci_scan_bridge_extend() - Scan buses behind a bridge
1250 * distributed equally between hotplug-capable bridges.
1258 * We need to process bridges in two passes -- first we scan those
1270 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge_extend()
1283 pm_runtime_get_sync(&dev->dev); in pci_scan_bridge_extend()
1290 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge_extend()
1293 if (!primary && (primary != bus->number) && secondary && subordinate) { in pci_scan_bridge_extend()
1295 primary = bus->number; in pci_scan_bridge_extend()
1300 (primary != bus->number || secondary <= bus->number || in pci_scan_bridge_extend()
1302 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge_extend()
1308 * Disable Master-Abort Mode during probing to avoid reporting of in pci_scan_bridge_extend()
1339 child->primary = primary; in pci_scan_bridge_extend()
1341 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1344 buses = subordinate - secondary; in pci_scan_bridge_extend()
1350 /* Subordinate should equal child->busn_res.end */ in pci_scan_bridge_extend()
1387 * This can happen when a bridge is hot-plugged, so in this in pci_scan_bridge_extend()
1388 * case we only re-scan this bus. in pci_scan_bridge_extend()
1396 bus->busn_res.end); in pci_scan_bridge_extend()
1400 available_buses--; in pci_scan_bridge_extend()
1403 | ((unsigned int)(child->primary) << 0) in pci_scan_bridge_extend()
1404 | ((unsigned int)(child->busn_res.start) << 8) in pci_scan_bridge_extend()
1405 | ((unsigned int)(child->busn_res.end) << 16); in pci_scan_bridge_extend()
1420 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1426 * cards with a PCI-to-PCI bridge can be inserted in pci_scan_bridge_extend()
1434 while (parent->parent) { in pci_scan_bridge_extend()
1436 (parent->busn_res.end > max) && in pci_scan_bridge_extend()
1437 (parent->busn_res.end <= max+i)) { in pci_scan_bridge_extend()
1440 parent = parent->parent; in pci_scan_bridge_extend()
1446 * bridges -- try to leave one in pci_scan_bridge_extend()
1467 sprintf(child->name, in pci_scan_bridge_extend()
1469 pci_domain_nr(bus), child->number); in pci_scan_bridge_extend()
1472 while (bus->parent) { in pci_scan_bridge_extend()
1473 if ((child->busn_res.end > bus->busn_res.end) || in pci_scan_bridge_extend()
1474 (child->number > bus->busn_res.end) || in pci_scan_bridge_extend()
1475 (child->number < bus->number) || in pci_scan_bridge_extend()
1476 (child->busn_res.end < bus->number)) { in pci_scan_bridge_extend()
1477 …dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", in pci_scan_bridge_extend()
1478 &child->busn_res); in pci_scan_bridge_extend()
1481 bus = bus->parent; in pci_scan_bridge_extend()
1487 pm_runtime_put(&dev->dev); in pci_scan_bridge_extend()
1493 * pci_scan_bridge() - Scan buses behind a bridge
1504 * We need to process bridges in two passes -- first we scan those
1519 * The architecture-dependent code can tweak these, of course.
1526 if (dev->is_virtfn) { in pci_read_irq()
1527 dev->pin = 0; in pci_read_irq()
1528 dev->irq = 0; in pci_read_irq()
1533 dev->pin = irq; in pci_read_irq()
1536 dev->irq = irq; in pci_read_irq()
1551 pdev->pcie_cap = pos; in set_pcie_port_type()
1553 pdev->pcie_flags_reg = reg16; in set_pcie_port_type()
1554 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); in set_pcie_port_type()
1555 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); in set_pcie_port_type()
1559 pdev->link_active_reporting = 1; in set_pcie_port_type()
1579 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1580 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; in set_pcie_port_type()
1590 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1591 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; in set_pcie_port_type()
1602 pdev->is_hotplug_bridge = 1; in set_pcie_hotplug_bridge()
1612 dev->is_thunderbolt = 1; in set_pcie_thunderbolt()
1624 if (parent && (parent->untrusted || parent->external_facing)) in set_pcie_untrusted()
1625 dev->untrusted = true; in set_pcie_untrusted()
1644 (parent->external_facing || dev_is_removable(&parent->dev))) in pci_set_removable()
1645 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); in pci_set_removable()
1649 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1652 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1661 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1686 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1689 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1717 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to in pci_cfg_space_size()
1721 * the fact that the SR-IOV capability on the PF resides in extended in pci_cfg_space_size()
1722 * config space and must be accessible and non-aliased to have enabled in pci_cfg_space_size()
1726 if (dev->is_virtfn) in pci_cfg_space_size()
1730 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_cfg_space_size()
1733 class = dev->class >> 8; in pci_cfg_space_size()
1756 if (dev->is_virtfn) in pci_class()
1757 return dev->physfn->sriov->class; in pci_class()
1766 if (dev->is_virtfn) { in pci_subsystem_ids()
1767 *vendor = dev->physfn->sriov->subsystem_vendor; in pci_subsystem_ids()
1768 *device = dev->physfn->sriov->subsystem_device; in pci_subsystem_ids()
1781 if (dev->is_virtfn) in pci_hdr_type()
1782 return dev->physfn->sriov->hdr_type; in pci_hdr_type()
1791 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1795 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1809 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI in pci_intx_mask_broken()
1842 "PCIe to PCI/PCI-X bridge", in pci_type_str()
1843 "PCI/PCI-X to PCIe bridge", in pci_type_str()
1857 switch (dev->hdr_type) { in pci_type_str()
1870 * pci_setup_device - Fill in class and map information of a device
1874 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1890 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1891 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1892 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1893 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1894 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1895 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1906 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) in pci_setup_device()
1909 dev->dma_mask = 0xffffffff; in pci_setup_device()
1911 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1912 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1913 PCI_FUNC(dev->devfn)); in pci_setup_device()
1917 dev->revision = class & 0xff; in pci_setup_device()
1918 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1923 /* Need to have dev->class ready */ in pci_setup_device()
1924 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1926 /* Need to have dev->cfg_size ready */ in pci_setup_device()
1932 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1940 dev->vendor, dev->device, dev->hdr_type, dev->class, in pci_setup_device()
1944 class = dev->class >> 8; in pci_setup_device()
1946 if (dev->non_compliant_bars && !dev->mmio_always_on) { in pci_setup_device()
1949 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1956 dev->broken_intx_masking = pci_intx_mask_broken(dev); in pci_setup_device()
1958 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1965 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); in pci_setup_device()
1970 * addresses. These are not always echoed in BAR0-3, and in pci_setup_device()
1971 * BAR0-3 in a few cases contain junk! in pci_setup_device()
1979 res = &dev->resource[0]; in pci_setup_device()
1980 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1981 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1986 res = &dev->resource[1]; in pci_setup_device()
1987 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1988 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1995 res = &dev->resource[2]; in pci_setup_device()
1996 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1997 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2002 res = &dev->resource[3]; in pci_setup_device()
2003 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
2004 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2013 * The PCI-to-PCI bridge spec requires that subtractive in pci_setup_device()
2018 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
2024 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
2025 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
2034 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
2035 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
2040 dev->hdr_type); in pci_setup_device()
2042 return -EIO; in pci_setup_device()
2046 dev->class, dev->hdr_type); in pci_setup_device()
2047 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
2062 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ in pci_configure_mps()
2063 if (dev->is_virtfn) in pci_configure_mps()
2074 mps = 128 << dev->pcie_mpss; in pci_configure_mps()
2105 mpss = 128 << dev->pcie_mpss; in pci_configure_mps()
2109 mpss, p_mps, 128 << bridge->pcie_mpss); in pci_configure_mps()
2145 host = pci_find_host_bridge(dev->bus); in pci_configure_extended_tags()
2153 if (host->no_ext_tags) { in pci_configure_extended_tags()
2171 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2191 if (dev->is_virtfn) in pci_configure_relaxed_ordering()
2199 * Ports. Peer-to-Peer DMA is another can of worms. in pci_configure_relaxed_ordering()
2205 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { in pci_configure_relaxed_ordering()
2215 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); in pci_configure_ltr()
2223 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); in pci_configure_ltr()
2232 dev->ltr_path = 1; in pci_configure_ltr()
2237 if (bridge && bridge->ltr_path) in pci_configure_ltr()
2238 dev->ltr_path = 1; in pci_configure_ltr()
2243 if (!host->native_ltr) in pci_configure_ltr()
2254 dev->ltr_path = 1; in pci_configure_ltr()
2259 * If we're configuring a hot-added device, LTR was likely in pci_configure_ltr()
2260 * disabled in the upstream bridge, so re-enable it before enabling in pci_configure_ltr()
2264 if (bridge && bridge->ltr_path) { in pci_configure_ltr()
2268 dev->ltr_path = 1; in pci_configure_ltr()
2290 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2293 if (bridge && bridge->eetlp_prefix_path) in pci_configure_eetlp_prefix()
2294 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2303 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_configure_serr()
2338 * pci_release_dev - Free a PCI device structure when all users of it are
2353 pci_bus_put(pci_dev->bus); in pci_release_dev()
2354 kfree(pci_dev->driver_override); in pci_release_dev()
2355 bitmap_free(pci_dev->dma_alias_mask); in pci_release_dev()
2368 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
2369 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
2370 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
2371 dev->driver_exclusive_resource = (struct resource) { in pci_alloc_dev()
2374 .end = -1, in pci_alloc_dev()
2377 spin_lock_init(&dev->pcie_cap_lock); in pci_alloc_dev()
2379 raw_spin_lock_init(&dev->msi_lock); in pci_alloc_dev()
2409 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2410 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2416 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2417 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2428 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2429 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2455 struct pci_dev *bridge = bus->self; in pci_bus_read_dev_vendor_id()
2461 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && in pci_bus_read_dev_vendor_id()
2462 bridge->device == 0x80b5) in pci_bus_read_dev_vendor_id()
2471 * Read the config data for a PCI device, sanity-check it,
2486 dev->devfn = devfn; in pci_scan_device()
2487 dev->vendor = l & 0xffff; in pci_scan_device()
2488 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
2491 pci_bus_put(dev->bus); in pci_scan_device()
2510 /* Multi-function PCIe devices share the same link/status */ in pcie_report_downtraining()
2511 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) in pcie_report_downtraining()
2522 pci_msix_init(dev); /* Disable MSI-X */ in pci_init_capabilities()
2524 /* Buffers for saving PCIe and PCI-X capabilities */ in pci_init_capabilities()
2529 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ in pci_init_capabilities()
2548 * per-device basis should be called from here.
2558 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
2579 * device-specific MSI domain, then inherit the default domain in pci_set_msi_domain()
2584 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
2586 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
2595 device_initialize(&dev->dev); in pci_device_add()
2596 dev->dev.release = pci_release_dev; in pci_device_add()
2598 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
2599 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
2600 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
2601 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
2603 dma_set_max_seg_size(&dev->dev, 65536); in pci_device_add()
2604 dma_set_seg_boundary(&dev->dev, 0xffffffff); in pci_device_add()
2613 dev->state_saved = false; in pci_device_add()
2618 * Add the device to our list of discovered devices in pci_device_add()
2622 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
2632 dev->match_driver = false; in pci_device_add()
2633 ret = device_add(&dev->dev); in pci_device_add()
2664 return -ENODEV; in next_ari_fn()
2668 return -ENODEV; in next_ari_fn()
2673 return -ENODEV; /* protect against malformed list */ in next_ari_fn()
2684 return -ENODEV; in next_fn()
2686 if (dev && !dev->multifunction) in next_fn()
2687 return -ENODEV; in next_fn()
2694 struct pci_dev *bridge = bus->self; in only_one_child()
2715 * pci_scan_slot - Scan a PCI slot on a bus for devices
2720 * discovered devices to the @bus->devices list. New devices
2739 dev->multifunction = 1; in pci_scan_slot()
2753 if (bus->self && nr) in pci_scan_slot()
2754 pcie_aspm_init_link_state(bus->self); in pci_scan_slot()
2769 * drivers attached. A hot-added device might support only the minimum in pcie_find_smpss()
2771 * where devices may be hot-added, we limit the fabric MPS to 128 so in pcie_find_smpss()
2772 * hot-added devices will work correctly. in pcie_find_smpss()
2774 * However, if we hot-add a device to a slot directly below a Root in pcie_find_smpss()
2777 * reconfigure MPS on both the Root Port and the hot-added device, in pcie_find_smpss()
2780 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. in pcie_find_smpss()
2782 if (dev->is_hotplug_bridge && in pcie_find_smpss()
2786 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
2787 *smpss = dev->pcie_mpss; in pcie_find_smpss()
2797 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
2800 dev->bus->self) in pcie_write_mps()
2815 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
2879 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
2886 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2894 if (!bus->self) in pcie_bus_configure_settings()
2897 if (!pci_is_pcie(bus->self)) in pcie_bus_configure_settings()
2901 * FIXME - Peer to peer DMA is possible, though the endpoint would need in pcie_bus_configure_settings()
2909 smpss = bus->self->pcie_mpss; in pcie_bus_configure_settings()
2911 pcie_find_smpss(bus->self, &smpss); in pcie_bus_configure_settings()
2915 pcie_bus_configure_set(bus->self, &smpss); in pcie_bus_configure_settings()
2930 * pci_scan_child_bus_extend() - Scan devices below a bus
2938 * equally between hotplug-capable bridges to allow future extension of the
2945 unsigned int start = bus->busn_res.start; in pci_scan_child_bus_extend()
2949 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus_extend()
2955 /* Reserve buses for SR-IOV capability */ in pci_scan_child_bus_extend()
2960 * After performing arch-dependent fixup of the bus, look behind in pci_scan_child_bus_extend()
2961 * all PCI-to-PCI bridges on this bus. in pci_scan_child_bus_extend()
2963 if (!bus->is_added) { in pci_scan_child_bus_extend()
2964 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus_extend()
2966 bus->is_added = 1; in pci_scan_child_bus_extend()
2975 if (dev->is_hotplug_bridge) in pci_scan_child_bus_extend()
2995 if (max - cmax > 1) in pci_scan_child_bus_extend()
2996 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
3011 } else if (dev->is_hotplug_bridge) { in pci_scan_child_bus_extend()
3017 buses = min(buses, available_buses - used_buses + 1); in pci_scan_child_bus_extend()
3022 /* One bus is already accounted so don't add it again */ in pci_scan_child_bus_extend()
3023 if (max - cmax > 1) in pci_scan_child_bus_extend()
3024 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
3032 if (bus->self && bus->self->is_hotplug_bridge) { in pci_scan_child_bus_extend()
3034 pci_hotplug_bus_size - 1); in pci_scan_child_bus_extend()
3035 if (max - start < used_buses) { in pci_scan_child_bus_extend()
3039 if (max > bus->busn_res.end) in pci_scan_child_bus_extend()
3040 max = bus->busn_res.end; in pci_scan_child_bus_extend()
3042 dev_dbg(&bus->dev, "%pR extended by %#02x\n", in pci_scan_child_bus_extend()
3043 &bus->busn_res, max - start); in pci_scan_child_bus_extend()
3052 * Return how far we've got finding sub-buses. in pci_scan_child_bus_extend()
3054 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus_extend()
3059 * pci_scan_child_bus() - Scan devices below a bus
3072 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3075 * Default empty implementation. Replace with an architecture-specific setup
3101 bridge->dev.parent = parent; in pci_create_root_bus()
3103 list_splice_init(resources, &bridge->windows); in pci_create_root_bus()
3104 bridge->sysdata = sysdata; in pci_create_root_bus()
3105 bridge->busnr = bus; in pci_create_root_bus()
3106 bridge->ops = ops; in pci_create_root_bus()
3112 return bridge->bus; in pci_create_root_bus()
3115 put_device(&bridge->dev); in pci_create_root_bus()
3127 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in pci_host_probe()
3131 bus = bridge->bus; in pci_host_probe()
3144 list_for_each_entry(child, &bus->children, node) in pci_host_probe()
3155 struct resource *res = &b->busn_res; in pci_bus_insert_busn_res()
3158 res->start = bus; in pci_bus_insert_busn_res()
3159 res->end = bus_max; in pci_bus_insert_busn_res()
3160 res->flags = IORESOURCE_BUS; in pci_bus_insert_busn_res()
3163 parent_res = &b->parent->busn_res; in pci_bus_insert_busn_res()
3166 res->flags |= IORESOURCE_PCI_FIXED; in pci_bus_insert_busn_res()
3172 dev_info(&b->dev, in pci_bus_insert_busn_res()
3175 parent_res, conflict->name, conflict); in pci_bus_insert_busn_res()
3182 struct resource *res = &b->busn_res; in pci_bus_update_busn_res_end()
3187 if (res->start > bus_max) in pci_bus_update_busn_res_end()
3188 return -EINVAL; in pci_bus_update_busn_res_end()
3190 size = bus_max - res->start + 1; in pci_bus_update_busn_res_end()
3191 ret = adjust_resource(res, res->start, size); in pci_bus_update_busn_res_end()
3192 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", in pci_bus_update_busn_res_end()
3195 if (!ret && !res->parent) in pci_bus_update_busn_res_end()
3196 pci_bus_insert_busn_res(b, res->start, res->end); in pci_bus_update_busn_res_end()
3203 struct resource *res = &b->busn_res; in pci_bus_release_busn_res()
3206 if (!res->flags || !res->parent) in pci_bus_release_busn_res()
3210 dev_info(&b->dev, "busn_res: %pR %s released\n", in pci_bus_release_busn_res()
3222 return -EINVAL; in pci_scan_root_bus_bridge()
3224 resource_list_for_each_entry(window, &bridge->windows) in pci_scan_root_bus_bridge()
3225 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus_bridge()
3226 bridge->busnr = window->res->start; in pci_scan_root_bus_bridge()
3235 b = bridge->bus; in pci_scan_root_bus_bridge()
3236 bus = bridge->busnr; in pci_scan_root_bus_bridge()
3239 dev_info(&b->dev, in pci_scan_root_bus_bridge()
3240 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus_bridge()
3263 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus()
3273 dev_info(&b->dev, in pci_scan_root_bus()
3274 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus()
3308 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3311 * Scan a PCI bus and child buses for new devices, add them,
3321 struct pci_bus *bus = bridge->subordinate; in pci_rescan_bus_bridge_resize()
3333 * pci_rescan_bus - Scan a PCI bus for devices
3336 * Scan a PCI bus and child buses for new devices, add them,
3377 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; in pci_sort_bf_cmp()
3378 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; in pci_sort_bf_cmp()
3380 if (a->bus->number < b->bus->number) return -1; in pci_sort_bf_cmp()
3381 else if (a->bus->number > b->bus->number) return 1; in pci_sort_bf_cmp()
3383 if (a->devfn < b->devfn) return -1; in pci_sort_bf_cmp()
3384 else if (a->devfn > b->devfn) return 1; in pci_sort_bf_cmp()
3396 struct pci_bus *parent = dev->bus; in pci_hp_add_bridge()
3397 int busnr, start = parent->busn_res.start; in pci_hp_add_bridge()
3399 int end = parent->busn_res.end; in pci_hp_add_bridge()
3405 if (busnr-- > end) { in pci_hp_add_bridge()
3406 pci_err(dev, "No bus number available for hot-added bridge\n"); in pci_hp_add_bridge()
3407 return -1; in pci_hp_add_bridge()
3414 * Distribute the available bus numbers between hotplug-capable in pci_hp_add_bridge()
3417 available_buses = end - busnr; in pci_hp_add_bridge()
3422 if (!dev->subordinate) in pci_hp_add_bridge()
3423 return -1; in pci_hp_add_bridge()