Lines Matching +full:parent +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0
52 struct pcie_link_state *parent; /* pointer to the parent Link state */ member
104 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
105 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
123 return link->aspm_default; in policy_to_aspm_state()
139 return link->clkpm_default; in policy_to_clkpm_state()
147 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
150 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_set_clkpm_nocheck()
154 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
163 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
166 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
177 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
180 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
191 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
192 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
193 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
194 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
206 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock() local
207 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
212 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
221 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
226 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
231 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
241 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n"); in pcie_aspm_configure_common_clock()
246 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
248 child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC; in pcie_aspm_configure_common_clock()
254 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
257 if (pcie_retrain_link(link->pdev, true)) { in pcie_aspm_configure_common_clock()
260 pci_err(parent, "ASPM: Could not configure common clock\n"); in pcie_aspm_configure_common_clock()
261 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
264 child_old_ccc[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
265 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
334 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max in encode_l12_threshold()
370 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
371 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
374 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
377 encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap); in pcie_aspm_check_latency()
381 encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap); in pcie_aspm_check_latency()
385 struct pci_dev *dev = pci_function_0(link->pdev->subordinate); in pcie_aspm_check_latency()
388 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, in pcie_aspm_check_latency()
398 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && in pcie_aspm_check_latency()
400 link->aspm_capable &= ~ASPM_STATE_L0S_UP; in pcie_aspm_check_latency()
403 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && in pcie_aspm_check_latency()
405 link->aspm_capable &= ~ASPM_STATE_L0S_DW; in pcie_aspm_check_latency()
420 if ((link->aspm_capable & ASPM_STATE_L1) && in pcie_aspm_check_latency()
422 link->aspm_capable &= ~ASPM_STATE_L1; in pcie_aspm_check_latency()
425 link = link->parent; in pcie_aspm_check_latency()
433 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info() local
451 if (calc_l12_pwron(parent, scale1, val1) > in aspm_calc_l12_info()
455 t_power_on = calc_l12_pwron(parent, scale1, val1); in aspm_calc_l12_info()
468 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l12_info()
469 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l12_info()
479 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); in aspm_calc_l12_info()
480 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); in aspm_calc_l12_info()
481 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); in aspm_calc_l12_info()
482 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2); in aspm_calc_l12_info()
494 child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
496 pci_clear_and_set_config_dword(parent, in aspm_calc_l12_info()
497 parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
502 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
503 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
506 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
510 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
514 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
520 pci_clear_and_set_config_dword(parent, in aspm_calc_l12_info()
521 parent->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
524 child->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
531 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_l1ss_init() local
535 if (!parent->l1ss || !child->l1ss) in aspm_l1ss_init()
539 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
541 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
554 if (!child->ltr_path) in aspm_l1ss_init()
558 link->aspm_support |= ASPM_STATE_L1_1; in aspm_l1ss_init()
560 link->aspm_support |= ASPM_STATE_L1_2; in aspm_l1ss_init()
562 link->aspm_support |= ASPM_STATE_L1_1_PCIPM; in aspm_l1ss_init()
564 link->aspm_support |= ASPM_STATE_L1_2_PCIPM; in aspm_l1ss_init()
567 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
570 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
574 link->aspm_enabled |= ASPM_STATE_L1_1; in aspm_l1ss_init()
576 link->aspm_enabled |= ASPM_STATE_L1_2; in aspm_l1ss_init()
578 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; in aspm_l1ss_init()
580 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; in aspm_l1ss_init()
582 if (link->aspm_support & ASPM_STATE_L1_2_MASK) in aspm_l1ss_init()
588 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init() local
591 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
595 link->aspm_enabled = ASPM_STATE_ALL; in pcie_aspm_cap_init()
596 link->aspm_disable = ASPM_STATE_ALL; in pcie_aspm_cap_init()
604 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
613 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
615 * read-only Link Capabilities may change depending on common clock in pcie_aspm_cap_init()
618 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
620 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); in pcie_aspm_cap_init()
631 link->aspm_support |= ASPM_STATE_L0S; in pcie_aspm_cap_init()
634 link->aspm_enabled |= ASPM_STATE_L0S_UP; in pcie_aspm_cap_init()
636 link->aspm_enabled |= ASPM_STATE_L0S_DW; in pcie_aspm_cap_init()
640 link->aspm_support |= ASPM_STATE_L1; in pcie_aspm_cap_init()
643 link->aspm_enabled |= ASPM_STATE_L1; in pcie_aspm_cap_init()
648 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
651 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
654 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
667 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss() local
669 enable_req = (link->aspm_enabled ^ state) & state; in pcie_config_aspm_l1ss()
673 * - When enabling L1.x, enable bit at parent first, then at child in pcie_config_aspm_l1ss()
674 * - When disabling L1.x, disable bit at child first, then at parent in pcie_config_aspm_l1ss()
675 * - When enabling ASPM L1.x, need to disable L1 in pcie_config_aspm_l1ss()
676 * (at child followed by parent). in pcie_config_aspm_l1ss()
677 * - The ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
685 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
687 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
696 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
711 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
713 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
726 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link() local
727 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
730 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
737 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
739 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
743 if (link->aspm_enabled == state) in pcie_config_aspm_link()
755 if (link->aspm_capable & ASPM_STATE_L1SS) in pcie_config_aspm_link()
765 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
766 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
769 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
771 link->aspm_enabled = state; in pcie_config_aspm_link()
778 link = link->parent; in pcie_config_aspm_path()
784 link->pdev->link_state = NULL; in free_link_state()
797 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
799 return -EINVAL; in pcie_aspm_sanity_check()
804 * pre-1.1 device in pcie_aspm_sanity_check()
811 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
816 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
817 return -EINVAL; in pcie_aspm_sanity_check()
831 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
832 link->pdev = pdev; in alloc_pcie_link_state()
833 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
836 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
844 !pdev->bus->parent->self) { in alloc_pcie_link_state()
845 link->root = link; in alloc_pcie_link_state()
847 struct pcie_link_state *parent; in alloc_pcie_link_state() local
849 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
850 if (!parent) { in alloc_pcie_link_state()
855 link->parent = parent; in alloc_pcie_link_state()
856 link->root = link->parent->root; in alloc_pcie_link_state()
859 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
860 pdev->link_state = link; in alloc_pcie_link_state()
868 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) in pcie_aspm_update_sysfs_visibility()
869 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group); in pcie_aspm_update_sysfs_visibility()
885 if (pdev->link_state) in pcie_aspm_init_link_state()
898 pdev->bus->self) in pcie_aspm_init_link_state()
902 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
945 BUG_ON(root->parent); in pcie_update_aspm_capable()
947 if (link->root != root) in pcie_update_aspm_capable()
949 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
953 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
954 if (link->root != root) in pcie_update_aspm_capable()
956 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
968 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state() local
971 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
977 link = parent->link_state; in pcie_aspm_exit_link_state()
978 root = link->root; in pcie_aspm_exit_link_state()
979 parent_link = link->parent; in pcie_aspm_exit_link_state()
982 * link->downstream is a pointer to the pci_dev of function 0. If in pcie_aspm_exit_link_state()
984 * so we can't use link->downstream again. Free the link state to in pcie_aspm_exit_link_state()
987 * If we're removing a non-0 function, it's possible we could in pcie_aspm_exit_link_state()
990 * multi-function devices, so disable ASPM for all of them. in pcie_aspm_exit_link_state()
993 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1008 * @locked: whether pci_bus_sem is held
1010 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) in pcie_aspm_pm_state_change() argument
1012 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_pm_state_change()
1020 if (!locked) in pcie_aspm_pm_state_change()
1023 pcie_update_aspm_capable(link->root); in pcie_aspm_pm_state_change()
1026 if (!locked) in pcie_aspm_pm_state_change()
1032 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1060 return bridge->link_state; in pcie_aspm_get_link()
1063 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool locked) in __pci_disable_link_state() argument
1068 return -EINVAL; in __pci_disable_link_state()
1079 return -EPERM; in __pci_disable_link_state()
1082 if (!locked) in __pci_disable_link_state()
1086 link->aspm_disable |= ASPM_STATE_L0S; in __pci_disable_link_state()
1089 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS; in __pci_disable_link_state()
1091 link->aspm_disable |= ASPM_STATE_L1_1; in __pci_disable_link_state()
1093 link->aspm_disable |= ASPM_STATE_L1_2; in __pci_disable_link_state()
1095 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM; in __pci_disable_link_state()
1097 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM; in __pci_disable_link_state()
1101 link->clkpm_disable = 1; in __pci_disable_link_state()
1104 if (!locked) in __pci_disable_link_state()
1119 * pci_disable_link_state - Disable device's link state, so the link will
1133 static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked) in __pci_enable_link_state() argument
1138 return -EINVAL; in __pci_enable_link_state()
1147 return -EPERM; in __pci_enable_link_state()
1150 if (!locked) in __pci_enable_link_state()
1153 link->aspm_default = 0; in __pci_enable_link_state()
1155 link->aspm_default |= ASPM_STATE_L0S; in __pci_enable_link_state()
1157 link->aspm_default |= ASPM_STATE_L1; in __pci_enable_link_state()
1160 link->aspm_default |= ASPM_STATE_L1_1 | ASPM_STATE_L1; in __pci_enable_link_state()
1162 link->aspm_default |= ASPM_STATE_L1_2 | ASPM_STATE_L1; in __pci_enable_link_state()
1164 link->aspm_default |= ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1; in __pci_enable_link_state()
1166 link->aspm_default |= ASPM_STATE_L1_2_PCIPM | ASPM_STATE_L1; in __pci_enable_link_state()
1169 link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0; in __pci_enable_link_state()
1172 if (!locked) in __pci_enable_link_state()
1179 * pci_enable_link_state - Clear and set the default device link state so that
1195 * pci_enable_link_state_locked - Clear and set the default device link state
1221 return -EPERM; in pcie_aspm_set_policy()
1256 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1271 return link->aspm_enabled; in pcie_aspm_enabled()
1282 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0); in aspm_attr_show_common()
1294 return -EINVAL; in aspm_attr_store_common()
1300 link->aspm_disable &= ~state; in aspm_attr_store_common()
1303 link->aspm_disable &= ~ASPM_STATE_L1; in aspm_attr_store_common()
1305 link->aspm_disable |= state; in aspm_attr_store_common()
1307 link->aspm_disable |= ASPM_STATE_L1SS; in aspm_attr_store_common()
1341 return sysfs_emit(buf, "%d\n", link->clkpm_enabled); in ASPM_ATTR()
1353 return -EINVAL; in clkpm_store()
1358 link->clkpm_disable = !state_enable; in clkpm_store()
1405 return link->clkpm_capable ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1407 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0; in aspm_ctrl_attrs_are_visible()