34 #define ASPM_STATE_L0S_DW	(2)	/* Downstream direction L0s state */
50 	struct pci_dev *downstream;	/* Downstream component, function 0 */  member
215 	/* Check downstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
245 	/* Configure downstream component, all functions */  in pcie_aspm_configure_common_clock()
402 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
433 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_calc_l12_info()
465 	 * downstream devices report (via LTR) that they can tolerate at  in aspm_calc_l12_info()
531 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_l1ss_init()
588 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_aspm_cap_init()
613 	 * Re-read upstream/downstream components' register state after  in pcie_aspm_cap_init()
667 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_l1ss()
726 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_link()
745 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
761 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
833 	link->downstream = pci_function_0(pdev->subordinate);  in alloc_pcie_link_state()
838 	 * the root ports entirely, in which case a downstream port on  in alloc_pcie_link_state()
875  * @pdev: the root port or switch downstream port
891 	 * downstream port.  in pcie_aspm_init_link_state()
982 	 * link->downstream is a pointer to the pci_dev of function 0.  If  in pcie_aspm_exit_link_state()
984 	 * so we can't use link->downstream again.  Free the link state to  in pcie_aspm_exit_link_state()
1007  * @pdev: the root port or switch downstream port