3  * Enable PCIe link L0s/L1 state and Clock Power Management
35 #define ASPM_STATE_L1		(4)	/* L1 state */
36 #define ASPM_STATE_L1_1		(8)	/* ASPM L1.1 state */
37 #define ASPM_STATE_L1_2		(0x10)	/* ASPM L1.2 state */
38 #define ASPM_STATE_L1_1_PCIPM	(0x20)	/* PCI PM L1.1 state */
39 #define ASPM_STATE_L1_2_PCIPM	(0x40)	/* PCI PM L1.2 state */
97  * The L1 PM substate capability is only implemented in function 0 in a
117 		/* Enable ASPM L0s/L1 */  in policy_to_aspm_state()
288 /* Convert L1 latency encoding to ns */
298 /* Convert L1 acceptable latency encoding to ns */
322  * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
323  * register.  Ports enter L1.2 when the most recent LTR value is greater
325  * don't enter L1.2 too aggressively.
380 	/* Calculate endpoint L1 acceptable latency */  in pcie_aspm_check_latency()
407 		 * Check L1 latency.  in pcie_aspm_check_latency()
409 		 * more microsecond for L1. Spec doesn't mention L0s.  in pcie_aspm_check_latency()
411 		 * The exit latencies for L1 substates are not advertised  in pcie_aspm_check_latency()
413 		 * to determine max latencies introduced by enabling L1  in pcie_aspm_check_latency()
415 		 * a L1 substate exit latency check.  We assume that the  in pcie_aspm_check_latency()
416 		 * L1 exit latencies advertised by a device include L1  in pcie_aspm_check_latency()
429 /* Calculate L1.2 PM substate timing parameters */
464 	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if  in aspm_calc_l12_info()
469 	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at  in aspm_calc_l12_info()
478 	/* Some broken devices only support dword access to L1 SS */  in aspm_calc_l12_info()
488 	/* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */  in aspm_calc_l12_info()
538 	/* Setup L1 substate */  in aspm_l1ss_init()
551 	 * to this device, we can't use ASPM L1.2 because it relies on the  in aspm_l1ss_init()
614 	 * clock configuration.  L0s & L1 exit latencies in the otherwise  in pcie_aspm_cap_init()
638 	/* Setup L1 state */  in pcie_aspm_cap_init()
663 /* Configure the ASPM L1 substates */
673 	 * - When enabling L1.x, enable bit at parent first, then at child  in pcie_config_aspm_l1ss()
674 	 * - When disabling L1.x, disable bit at child first, then at parent  in pcie_config_aspm_l1ss()
675 	 * - When enabling ASPM L1.x, need to disable L1  in pcie_config_aspm_l1ss()
677 	 * - The ASPM/PCIPM L1.2 must be disabled while programming timing  in pcie_config_aspm_l1ss()
684 	/* Disable all L1 substates */  in pcie_config_aspm_l1ss()
690 	 * If needed, disable L1, and it gets enabled later  in pcie_config_aspm_l1ss()
732 	/* Can't enable any substates if L1 is not enabled */  in pcie_config_aspm_link()
760 	 * same setting for ASPM. Enabling ASPM L1 should be done in  in pcie_config_aspm_link()
762 	 * versa for disabling ASPM L1. Spec doesn't mention L0S.  in pcie_config_aspm_link()
1088 		/* L1 PM substates require L1 */  in __pci_disable_link_state()
1158 	/* L1 PM substates require L1 */  in __pci_enable_link_state()
1301 		/* need to enable L1 for substates */  in aspm_attr_store_common()
1329 ASPM_ATTR(l1_aspm, L1)  in ASPM_ATTR()