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1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
45 int isa_dma_bridge_buggy;
49 int pci_pci_problems;
52 unsigned int pci_pm_d3hot_delay;
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
85 unsigned int upper; in pci_dev_d3_sleep()
97 return dev->reset_methods[0] != 0; in pci_reset_supported()
101 int pci_domains_supported = 1;
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
141 * The default CLS is used if arch didn't set CLS explicitly and not
144 * measured in 32-bit words, not bytes.
153 unsigned int pcibios_max_latency = 255;
175 static int __init pcie_port_pm_setup(char *str) in pcie_port_pm_setup()
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
190 * including the given PCI bus and its list of child PCI buses.
197 max = bus->busn_res.end; in pci_bus_max_busnr()
198 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
211 * Returns error bits set in PCI_STATUS and clears them.
213 int pci_status_get_and_clear_errors(struct pci_dev *pdev) in pci_status_get_and_clear_errors()
216 int ret; in pci_status_get_and_clear_errors()
220 return -EIO; in pci_status_get_and_clear_errors()
231 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar, in __pci_ioremap_resource()
234 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
235 resource_size_t start = res->start; in __pci_ioremap_resource()
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
252 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) in pci_ioremap_bar()
258 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) in pci_ioremap_wc_bar()
266 * pci_dev_str_match_path - test if a path string matches a device
277 * A path for a device can be obtained using 'lspci -t'. Using a path
279 * device and function address.
281 * Returns 1 if the string matches the device, 0 if it does not and
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, in pci_dev_str_match_path()
287 int ret; in pci_dev_str_match_path()
288 unsigned int seg, bus, slot, func; in pci_dev_str_match_path()
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
296 return -ENOMEM; in pci_dev_str_match_path()
304 ret = -EINVAL; in pci_dev_str_match_path()
308 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
317 * and so on. in pci_dev_str_match_path()
334 ret = -EINVAL; in pci_dev_str_match_path()
339 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
340 bus == dev->bus->number && in pci_dev_str_match_path()
341 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
349 * pci_dev_str_match - test if a string matches a device
366 * through the use of 'lspci -t'.
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
372 * legacy reasons and convenience so users don't have to specify
375 * Returns 1 if the string matches the device, 0 if it does not and
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p, in pci_dev_str_match()
381 int ret; in pci_dev_str_match()
382 int count; in pci_dev_str_match()
393 return -EINVAL; in pci_dev_str_match()
401 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
402 (!device || device == dev->device) && in pci_dev_str_match()
404 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
406 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap_ttl()
429 u8 pos, int cap, int *ttl) in __pci_find_next_cap_ttl()
436 while ((*ttl)--) { in __pci_find_next_cap_ttl()
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap()
453 u8 pos, int cap) in __pci_find_next_cap()
455 int ttl = PCI_FIND_CAP_TTL; in __pci_find_next_cap()
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) in pci_find_next_capability()
462 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
468 unsigned int devfn, u8 hdr_type) in __pci_bus_find_cap_start()
488 * pci_find_capability - query for devices' capabilities
495 * support it. Possible values for @cap include:
503 * %PCI_CAP_ID_PCIX PCI-X
506 u8 pci_find_capability(struct pci_dev *dev, int cap) in pci_find_capability()
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
519 * pci_bus_find_capability - query for devices' capabilities
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) in pci_bus_find_capability()
546 * pci_find_next_ext_capability - Find an extended capability
554 * vendor-specific capability, and this provides a way to find them all.
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) in pci_find_next_ext_capability()
559 int ttl; in pci_find_next_ext_capability()
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
576 * cap version and next pointer all being 0. in pci_find_next_ext_capability()
581 while (ttl-- > 0) { in pci_find_next_ext_capability()
598 * pci_find_ext_capability - Find an extended capability
604 * not support it. Possible values for @cap include:
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap) in pci_find_ext_capability()
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
621 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
630 int pos; in pci_get_dsn()
639 * the lower half, and the second dword is the upper half. in pci_get_dsn()
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) in __pci_find_next_ht_cap()
653 int rc, ttl = PCI_FIND_CAP_TTL; in __pci_find_next_ht_cap()
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) in pci_find_next_ht_capability()
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) in pci_find_ht_capability()
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
725 * @cap: Vendor-specific capability ID
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) in pci_find_vsec_capability()
735 int ret; in pci_find_vsec_capability()
737 if (vendor != dev->vendor) in pci_find_vsec_capability()
755 * pci_find_dvsec_capability - Find DVSEC for vendor
758 * @dvsec: Designated Vendor-specific capability ID
760 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
765 int pos; in pci_find_dvsec_capability()
787 * pci_find_parent_resource - return resource region of parent bus of given
798 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
810 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
811 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
816 * be both a positively-decoded aperture and a in pci_find_parent_resource()
817 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
818 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
830 * pci_find_resource - Return matching PCI device resource
834 * Goes over standard PCI resources (BARs) and checks if the given resource
840 int i; in pci_find_resource()
843 struct resource *r = &dev->resource[i]; in pci_find_resource()
845 if (r->start && resource_contains(r, res)) in pci_find_resource()
854 * pci_resource_name - Return the name of the PCI resource
860 const char *pci_resource_name(struct pci_dev *dev, unsigned int i) in pci_resource_name()
903 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS && in pci_resource_name()
914 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
921 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) in pci_wait_for_pending()
923 int i; in pci_wait_for_pending()
929 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
939 static int pci_acs_enable;
942 * pci_request_acs - ask for ACS to be enabled if supported
952 * pci_disable_acs_redir - disable ACS redirect capabilities
959 int ret = 0; in pci_disable_acs_redir()
961 int pos; in pci_disable_acs_redir()
993 pos = dev->acs_cap; in pci_disable_acs_redir()
1010 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1015 int pos; in pci_std_enable_acs()
1019 pos = dev->acs_cap; in pci_std_enable_acs()
1038 /* Enable Translation Blocking for external devices and noats */ in pci_std_enable_acs()
1039 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
1046 * pci_enable_acs - enable ACS if hardware support it
1071 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1074 * Restore the BAR values for a given device, so as to make it
1079 int i; in pci_restore_bars()
1093 static inline int platform_pci_set_power_state(struct pci_dev *dev, in platform_pci_set_power_state()
1124 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) in platform_pci_set_wakeup()
1149 * pci_update_current_state - Read power state of given device and cache it
1163 dev->current_state = PCI_D3cold; in pci_update_current_state()
1164 } else if (dev->pm_cap) { in pci_update_current_state()
1167 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1169 dev->current_state = PCI_D3cold; in pci_update_current_state()
1172 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1174 dev->current_state = state; in pci_update_current_state()
1179 * pci_refresh_power_state - Refresh the given device's power state data
1182 * Ask the platform to refresh the devices power state information and invoke
1188 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1192 * pci_platform_power_transition - Use platform to change device power state
1196 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) in pci_platform_power_transition()
1198 int error; in pci_platform_power_transition()
1203 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1204 dev->current_state = PCI_D0; in pci_platform_power_transition()
1210 static int pci_resume_one(struct pci_dev *pci_dev, void *ign) in pci_resume_one()
1212 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1217 * pci_resume_bus - Walk given bus and runtime resume devices on it
1226 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) in pci_dev_wait()
1228 int delay = 1; in pci_dev_wait()
1243 * the read (except when CRS SV is enabled and the read was for the in pci_dev_wait()
1246 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1259 delay - 1, reset_type); in pci_dev_wait()
1260 return -ENOTTY; in pci_dev_wait()
1272 delay - 1, reset_type); in pci_dev_wait()
1280 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1283 pci_dbg(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1290 * pci_power_up - Put the given device into D0
1298 * put the device in D0 via non-PCI means.
1300 int pci_power_up(struct pci_dev *dev) in pci_power_up()
1308 if (!dev->pm_cap) { in pci_power_up()
1311 dev->current_state = PCI_D0; in pci_power_up()
1313 dev->current_state = state; in pci_power_up()
1315 return -EIO; in pci_power_up()
1318 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1321 pci_power_name(dev->current_state)); in pci_power_up()
1322 dev->current_state = PCI_D3cold; in pci_power_up()
1323 return -EIO; in pci_power_up()
1328 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1336 * PME_En, and sets PowerState to 0. in pci_power_up()
1338 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1347 dev->current_state = PCI_D0; in pci_power_up()
1355 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1360 * to confirm the state change, restore its BARs if they might be lost and
1367 static int pci_set_full_power_state(struct pci_dev *dev, bool locked) in pci_set_full_power_state()
1370 int ret; in pci_set_full_power_state()
1374 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1380 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1381 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1382 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1384 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1391 * For example, at least some versions of the 3c905B and the in pci_set_full_power_state()
1402 if (dev->bus->self) in pci_set_full_power_state()
1403 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_full_power_state()
1409 * __pci_dev_set_current_state - Set current state of a PCI device
1413 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) in __pci_dev_set_current_state()
1417 dev->current_state = state; in __pci_dev_set_current_state()
1422 * pci_bus_set_current_state - Walk given bus and set current state of devices
1444 * pci_set_low_power_state - Put a PCI device into a low-power state.
1449 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1452 * -EINVAL if the requested state is invalid.
1453 * -EIO if device does not support PCI PM or its PM capabilities register has a
1458 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state, bool locked) in pci_set_low_power_state()
1462 if (!dev->pm_cap) in pci_set_low_power_state()
1463 return -EIO; in pci_set_low_power_state()
1467 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1471 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1473 pci_power_name(dev->current_state), in pci_set_low_power_state()
1475 return -EINVAL; in pci_set_low_power_state()
1479 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1480 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1481 return -EIO; in pci_set_low_power_state()
1483 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1486 pci_power_name(dev->current_state), in pci_set_low_power_state()
1488 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1489 return -EIO; in pci_set_low_power_state()
1496 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1504 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1505 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1506 if (dev->current_state != state) in pci_set_low_power_state()
1508 pci_power_name(dev->current_state), in pci_set_low_power_state()
1511 if (dev->bus->self) in pci_set_low_power_state()
1512 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_low_power_state()
1517 static int __pci_set_power_state(struct pci_dev *dev, pci_power_t state, bool locked) in __pci_set_power_state()
1519 int error; in __pci_set_power_state()
1537 if (dev->current_state == state) in __pci_set_power_state()
1547 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in __pci_set_power_state()
1561 if (dev->current_state == PCI_D3cold) in __pci_set_power_state()
1562 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked); in __pci_set_power_state()
1574 * pci_set_power_state - Set the power state of a PCI device
1578 * Transition a device to a new power state, using the platform firmware and/or
1582 * -EINVAL if the requested state is invalid.
1583 * -EIO if device does not support PCI PM or its PM capabilities register has a
1585 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1590 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_power_state()
1596 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) in pci_set_power_state_locked()
1611 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1612 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1628 static int pci_save_pcie_state(struct pci_dev *dev) in pci_save_pcie_state()
1630 int i = 0; in pci_save_pcie_state()
1640 return -ENOMEM; in pci_save_pcie_state()
1643 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1662 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1665 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1675 int i = 0; in pci_restore_pcie_state()
1685 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1690 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1700 static int pci_save_pcix_state(struct pci_dev *dev) in pci_save_pcix_state()
1702 int pos; in pci_save_pcix_state()
1712 return -ENOMEM; in pci_save_pcix_state()
1716 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1723 int i = 0, pos; in pci_restore_pcix_state()
1731 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1738 int ltr; in pci_save_ltr_state()
1756 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
1763 int ltr; in pci_restore_ltr_state()
1772 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
1777 * pci_save_state - save the PCI configuration space of a device before
1781 int pci_save_state(struct pci_dev *dev) in pci_save_state()
1783 int i; in pci_save_state()
1786 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1788 i * 4, dev->saved_config_space[i]); in pci_save_state()
1790 dev->state_saved = true; in pci_save_state()
1808 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, in pci_restore_config_dword()
1809 u32 saved_val, int retry, bool force) in pci_restore_config_dword()
1818 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1821 if (retry-- <= 0) in pci_restore_config_dword()
1833 int start, int end, int retry, in pci_restore_config_space_range()
1836 int index; in pci_restore_config_space_range()
1838 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1840 pdev->saved_config_space[index], in pci_restore_config_space_range()
1846 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1851 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1868 unsigned int pos, nbars, i; in pci_restore_rebar_state()
1880 int bar_idx, size; in pci_restore_rebar_state()
1884 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1893 * pci_restore_state - Restore the saved state of a PCI device
1898 if (!dev->state_saved) in pci_restore_state()
1924 /* Restore ACS and IOV configuration state */ in pci_restore_state()
1928 dev->state_saved = false; in pci_restore_state()
1938 * pci_store_saved_state - Allocate and return an opaque struct containing
1951 if (!dev->state_saved) in pci_store_saved_state()
1956 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1957 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1963 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1964 sizeof(state->config_space)); in pci_store_saved_state()
1966 cap = state->cap; in pci_store_saved_state()
1967 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1968 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1969 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1979 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1983 int pci_load_saved_state(struct pci_dev *dev, in pci_load_saved_state()
1988 dev->state_saved = false; in pci_load_saved_state()
1993 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1994 sizeof(state->config_space)); in pci_load_saved_state()
1996 cap = state->cap; in pci_load_saved_state()
1997 while (cap->size) { in pci_load_saved_state()
2000 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
2001 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
2002 return -EINVAL; in pci_load_saved_state()
2004 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
2006 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
2009 dev->state_saved = true; in pci_load_saved_state()
2015 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2016 * and free the memory allocated for it.
2020 int pci_load_and_free_saved_state(struct pci_dev *dev, in pci_load_and_free_saved_state()
2023 int ret = pci_load_saved_state(dev, *state); in pci_load_and_free_saved_state()
2030 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) in pcibios_enable_device()
2035 static int do_pci_enable_device(struct pci_dev *dev, int bars) in do_pci_enable_device()
2037 int err; in do_pci_enable_device()
2043 if (err < 0 && err != -EIO) in do_pci_enable_device()
2055 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
2070 * pci_reenable_device - Resume abandoned device
2073 * NOTE: This function is a backend of pci_default_resume() and is not supposed
2074 * to be called by normal code, write proper resume handler and use it instead.
2076 int pci_reenable_device(struct pci_dev *dev) in pci_reenable_device()
2079 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
2087 int retval; in pci_enable_bridge()
2094 if (!dev->is_busmaster) in pci_enable_bridge()
2106 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) in pci_enable_device_flags()
2109 int err; in pci_enable_device_flags()
2110 int i, bars = 0; in pci_enable_device_flags()
2118 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2120 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2129 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2132 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2137 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2142 * pci_enable_device_io - Initialize a device for use with IO space
2145 * Initialize device before it's used by a driver. Ask low-level code
2149 int pci_enable_device_io(struct pci_dev *dev) in pci_enable_device_io()
2156 * pci_enable_device_mem - Initialize a device for use with Memory space
2159 * Initialize device before it's used by a driver. Ask low-level code
2163 int pci_enable_device_mem(struct pci_dev *dev) in pci_enable_device_mem()
2170 * pci_enable_device - Initialize device before it's used by a driver.
2173 * Initialize device before it's used by a driver. Ask low-level code
2174 * to enable I/O and memory. Wake up the device if it was suspended.
2180 int pci_enable_device(struct pci_dev *dev) in pci_enable_device()
2187 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2188 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2193 unsigned int enabled:1;
2194 unsigned int pinned:1;
2195 unsigned int orig_intx:1;
2196 unsigned int restore_intx:1;
2197 unsigned int mwi:1;
2205 int i; in pcim_release()
2208 if (this->region_mask & (1 << i)) in pcim_release()
2211 if (this->mwi) in pcim_release()
2214 if (this->restore_intx) in pcim_release()
2215 pci_intx(dev, this->orig_intx); in pcim_release()
2217 if (this->enabled && !this->pinned) in pcim_release()
2225 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2232 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2238 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2243 * pcim_enable_device - Managed pci_enable_device()
2248 int pcim_enable_device(struct pci_dev *pdev) in pcim_enable_device()
2251 int rc; in pcim_enable_device()
2255 return -ENOMEM; in pcim_enable_device()
2256 if (dr->enabled) in pcim_enable_device()
2261 pdev->is_managed = 1; in pcim_enable_device()
2262 dr->enabled = 1; in pcim_enable_device()
2269 * pcim_pin_device - Pin managed PCI device
2281 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2283 dr->pinned = 1; in pcim_pin_device()
2288 * pcibios_device_add - provide arch specific hooks when adding device dev
2295 int __weak pcibios_device_add(struct pci_dev *dev) in pcibios_device_add()
2301 * pcibios_release_device - provide arch specific hooks when releasing
2312 * pcibios_disable_device - disable arch specific PCI resources for device dev
2322 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2326 * Permits the platform to provide architecture-specific functionality when
2330 void __weak pcibios_penalize_isa_irq(int irq, int active) {} in pcibios_penalize_isa_irq()
2346 * pci_disable_enabled_device - Disable device without updating enable_cnt
2349 * NOTE: This function is a backend of PCI power management routines and is
2359 * pci_disable_device - Disable PCI device after use
2363 * anymore. This only involves disabling PCI bus-mastering, if active.
2374 dr->enabled = 0; in pci_disable_device()
2376 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2377 "disabling already-disabled device"); in pci_disable_device()
2379 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2384 dev->is_busmaster = 0; in pci_disable_device()
2389 * pcibios_set_pcie_reset_state - set reset state for device dev
2396 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, in pcibios_set_pcie_reset_state()
2399 return -EINVAL; in pcibios_set_pcie_reset_state()
2403 * pci_set_pcie_reset_state - set reset state for device dev
2409 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) in pci_set_pcie_reset_state()
2426 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2435 * pci_check_pme_status - Check if given device has generated PME.
2438 * Check the PME status of the device and if set, clear it and clear PME enable
2439 * (if set). Return 'true' if PME status and PME enable were both set or
2444 int pmcsr_pos; in pci_check_pme_status()
2448 if (!dev->pm_cap) in pci_check_pme_status()
2451 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2470 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2474 * Check if @dev has generated PME and queue a resume request for it in that
2477 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) in pci_pme_wakeup()
2479 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2480 dev->pme_poll = false; in pci_pme_wakeup()
2484 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2490 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2501 * pci_pme_capable - check the capability of PCI device to generate PME#
2507 if (!dev->pm_cap) in pci_pme_capable()
2510 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2520 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2522 if (pdev->pme_poll) { in pci_pme_list_scan()
2523 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2524 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2525 struct device *bdev = bridge ? &bridge->dev : NULL; in pci_pme_list_scan()
2526 int bref = 0; in pci_pme_list_scan()
2539 if (bridge->current_state != PCI_D0) in pci_pme_list_scan()
2549 pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2556 list_del(&pme_dev->list); in pci_pme_list_scan()
2570 if (!dev->pme_support) in __pci_pme_active()
2573 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2574 /* Clear PME_Status by writing 1 to it and enable PME# */ in __pci_pme_active()
2579 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2583 * pci_pme_restore - Restore PME configuration after config space restore.
2590 if (!dev->pme_support) in pci_pme_restore()
2593 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2594 if (dev->wakeup_prepared) { in pci_pme_restore()
2601 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2605 * pci_pme_active - enable or disable PCI device's PME# function
2619 * do this, so the PME never gets delivered and the device in pci_pme_active()
2621 * periodically walk the list of suspended devices and check in pci_pme_active()
2624 * hit, and the power savings from the devices will still be a in pci_pme_active()
2627 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2636 if (dev->pme_poll) { in pci_pme_active()
2645 pme_dev->dev = dev; in pci_pme_active()
2647 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2656 if (pme_dev->dev == dev) { in pci_pme_active()
2657 list_del(&pme_dev->list); in pci_pme_active()
2671 * __pci_enable_wake - enable PCI device as wakeup event source
2677 * When such events involves platform-specific hooks, those hooks are
2685 * -EINVAL is returned if device is not supposed to wake up the system
2686 * Error code depending on the platform is returned if both the platform and
2687 * the native mechanism fail to enable the generation of wake-up events
2689 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) in __pci_enable_wake()
2691 int ret = 0; in __pci_enable_wake()
2694 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2697 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2698 * on a hotplug event) and they need to be covered here. in __pci_enable_wake()
2704 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2710 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2714 int error; in __pci_enable_wake()
2720 * signal PME when the hierarchy above it goes into D3cold and in __pci_enable_wake()
2731 dev->wakeup_prepared = true; in __pci_enable_wake()
2735 dev->wakeup_prepared = false; in __pci_enable_wake()
2742 * pci_enable_wake - change wakeup settings for a PCI device
2750 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) in pci_enable_wake()
2752 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2753 return -EINVAL; in pci_enable_wake()
2760 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2762 * @enable: True to enable wake-up event generation; false to disable
2765 * and this function allows them to set that up cleanly - pci_enable_wake()
2766 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2771 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2773 int pci_wake_from_d3(struct pci_dev *dev, bool enable) in pci_wake_from_d3()
2782 * pci_target_state - find an appropriate low power state for a given PCI dev
2813 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2814 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2817 if (dev->current_state == PCI_D3cold) in pci_target_state()
2819 else if (!dev->pm_cap) in pci_target_state()
2822 if (wakeup && dev->pme_support) { in pci_target_state()
2829 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2830 state--; in pci_target_state()
2834 else if (dev->pme_support & 1) in pci_target_state()
2842 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2847 * it can wake up the system and/or is power manageable by the platform
2848 * (PCI_D3hot is the default) and put the device into that state.
2850 int pci_prepare_to_sleep(struct pci_dev *dev) in pci_prepare_to_sleep()
2852 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2854 int error; in pci_prepare_to_sleep()
2857 return -EIO; in pci_prepare_to_sleep()
2871 * pci_back_from_sleep - turn PCI device on during system-wide transition
2875 * Disable device's system wake-up capability and put it into D0.
2877 int pci_back_from_sleep(struct pci_dev *dev) in pci_back_from_sleep()
2879 int ret = pci_set_power_state(dev, PCI_D0); in pci_back_from_sleep()
2890 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2893 * Prepare @dev to generate wake-up events at run time and put it into a low
2896 int pci_finish_runtime_suspend(struct pci_dev *dev) in pci_finish_runtime_suspend()
2899 int error; in pci_finish_runtime_suspend()
2901 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2903 return -EIO; in pci_finish_runtime_suspend()
2916 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2919 * Return true if the device itself is capable of generating wake-up events
2921 * PME and one of its upstream bridges can generate wake-up events.
2925 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2927 if (!dev->pme_support) in pci_dev_run_wake()
2930 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2934 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2937 while (bus->parent) { in pci_dev_run_wake()
2938 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2940 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2943 bus = bus->parent; in pci_dev_run_wake()
2947 if (bus->bridge) in pci_dev_run_wake()
2948 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2955 * pci_dev_need_resume - Check if it is necessary to resume the device.
2958 * Return 'true' if the device is not runtime-suspended or it has to be
2959 * reconfigured due to wakeup settings difference between system and runtime
2961 * (system-wide) transition.
2965 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2978 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2980 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2984 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2987 * If the device is suspended and it is not configured for system wakeup,
2990 * Note that if the device's power state is D3cold and the platform check in
2996 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2998 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
3001 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
3004 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
3008 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
3011 * If the device is runtime suspended and wakeup-capable, enable PME for it as
3017 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
3022 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
3024 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
3027 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
3031 * pci_choose_state - Choose the power state of a PCI device.
3035 * Returns PCI power state suitable for @dev and @state.
3048 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
3049 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
3055 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
3064 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
3070 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
3071 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
3087 .ident = "X299 DESIGNARE EX-CF",
3090 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3096 * into D3cold and back into D0 on Elo Continental Z2 board
3110 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3114 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3130 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3132 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3139 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3151 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3169 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) in pci_dev_check_d3cold()
3174 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3176 /* ... and if it is wakeup capable to do so from D3cold. */ in pci_dev_check_d3cold()
3177 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3189 * pci_bridge_d3_update - Update bridge D3 capabilities
3198 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3210 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3214 * If D3 is currently allowed for the bridge and a child is added or in pci_bridge_d3_update()
3230 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3231 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3234 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3235 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3242 * pci_d3cold_enable - Enable D3cold for device
3251 if (dev->no_d3cold) { in pci_d3cold_enable()
3252 dev->no_d3cold = false; in pci_d3cold_enable()
3259 * pci_d3cold_disable - Disable D3cold for device
3268 if (!dev->no_d3cold) { in pci_d3cold_disable()
3269 dev->no_d3cold = true; in pci_d3cold_disable()
3276 * pci_pm_init - Initialize PM functions of given PCI device
3281 int pm; in pci_pm_init()
3285 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3286 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3287 pm_runtime_enable(&dev->dev); in pci_pm_init()
3288 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3289 dev->wakeup_prepared = false; in pci_pm_init()
3291 dev->pm_cap = 0; in pci_pm_init()
3292 dev->pme_support = 0; in pci_pm_init()
3307 dev->pm_cap = pm; in pci_pm_init()
3308 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3309 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3310 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3311 dev->d3cold_allowed = true; in pci_pm_init()
3313 dev->d1_support = false; in pci_pm_init()
3314 dev->d2_support = false; in pci_pm_init()
3317 dev->d1_support = true; in pci_pm_init()
3319 dev->d2_support = true; in pci_pm_init()
3321 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3323 dev->d1_support ? " D1" : "", in pci_pm_init()
3324 dev->d2_support ? " D2" : ""); in pci_pm_init()
3335 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc); in pci_pm_init()
3336 dev->pme_poll = true; in pci_pm_init()
3338 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3341 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3348 dev->imm_ready = 1; in pci_pm_init()
3378 return &dev->resource[bei]; in pci_ea_get_resource()
3382 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3383 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3386 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3392 static int pci_ea_read(struct pci_dev *dev, int offset) in pci_ea_read()
3396 int ent_size, ent_offset = offset; in pci_ea_read()
3446 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3455 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3465 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3487 if (ent_size != ent_offset - offset) { in pci_ea_read()
3488 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", in pci_ea_read()
3489 ent_size, ent_offset - offset); in pci_ea_read()
3493 res->name = pci_name(dev); in pci_ea_read()
3494 res->start = start; in pci_ea_read()
3495 res->end = end; in pci_ea_read()
3496 res->flags = flags; in pci_ea_read()
3518 int ea; in pci_ea_init()
3520 int offset; in pci_ea_init()
3521 int i; in pci_ea_init()
3529 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3536 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3547 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3551 * _pci_add_cap_save_buffer - allocate buffer for saving given
3558 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, in _pci_add_cap_save_buffer()
3559 bool extended, unsigned int size) in _pci_add_cap_save_buffer()
3561 int pos; in _pci_add_cap_save_buffer()
3574 return -ENOMEM; in _pci_add_cap_save_buffer()
3576 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3577 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3578 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3584 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) in pci_add_cap_save_buffer()
3589 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) in pci_add_ext_cap_save_buffer()
3595 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3600 int error; in pci_allocate_cap_save_buffers()
3609 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3624 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3629 * pci_configure_ari - enable or disable ARI forwarding
3632 * If @dev and its upstream bridge both support ARI, enable ARI in the
3640 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3643 bridge = dev->bus->self; in pci_configure_ari()
3654 bridge->ari_enabled = 1; in pci_configure_ari()
3658 bridge->ari_enabled = 0; in pci_configure_ari()
3664 int pos; in pci_acs_flags_enabled()
3667 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3674 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3684 * pci_acs_enabled - test ACS against required flags for a given device
3694 * opportunity for peer-to-peer access. We therefore return 'true'
3701 int ret; in pci_acs_enabled()
3708 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3717 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3719 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3732 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should in pci_acs_enabled()
3733 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3734 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3741 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3750 if (!pdev->multifunction) in pci_acs_enabled()
3764 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3783 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3786 parent = pdev->bus->self; in pci_acs_path_enabled()
3793 * pci_acs_init - Initialize ACS if hardware supports it
3798 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3810 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3815 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3816 * Returns -ENOENT if no ctrl register for the BAR could be found.
3818 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) in pci_rebar_find_pos()
3820 unsigned int pos, nbars, i; in pci_rebar_find_pos()
3825 return -ENOTSUPP; in pci_rebar_find_pos()
3831 int bar_idx; in pci_rebar_find_pos()
3839 return -ENOENT; in pci_rebar_find_pos()
3843 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3850 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) in pci_rebar_get_possible_sizes()
3852 int pos; in pci_rebar_get_possible_sizes()
3863 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3872 * pci_rebar_get_current_size - get the current size of a BAR
3879 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) in pci_rebar_get_current_size()
3881 int pos; in pci_rebar_get_current_size()
3893 * pci_rebar_set_size - set a new size for a BAR
3901 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) in pci_rebar_set_size()
3903 int pos; in pci_rebar_set_size()
3918 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3926 * blocking is disabled on all upstream ports, and the root port supports
3927 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3930 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) in pci_enable_atomic_ops_to_root()
3932 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3938 * in Device Control 2 is reserved in VFs and the PF value applies in pci_enable_atomic_ops_to_root()
3941 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3942 return -EINVAL; in pci_enable_atomic_ops_to_root()
3945 return -EINVAL; in pci_enable_atomic_ops_to_root()
3948 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be in pci_enable_atomic_ops_to_root()
3950 * requesters and root ports as completers. No endpoints as in pci_enable_atomic_ops_to_root()
3951 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3960 return -EINVAL; in pci_enable_atomic_ops_to_root()
3963 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3964 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3973 return -EINVAL; in pci_enable_atomic_ops_to_root()
3979 return -EINVAL; in pci_enable_atomic_ops_to_root()
3988 return -EINVAL; in pci_enable_atomic_ops_to_root()
3991 bus = bus->parent; in pci_enable_atomic_ops_to_root()
4001 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
4006 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
4007 * behind bridges on add-in cards. For devices with ARI enabled, the slot
4013 int slot; in pci_swizzle_interrupt_pin()
4015 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
4018 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
4020 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
4023 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) in pci_get_interrupt_pin()
4027 pin = dev->pin; in pci_get_interrupt_pin()
4029 return -1; in pci_get_interrupt_pin()
4031 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
4033 dev = dev->bus->self; in pci_get_interrupt_pin()
4040 * pci_common_swizzle - swizzle INTx all the way to root bridge
4044 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4051 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
4053 dev = dev->bus->self; in pci_common_swizzle()
4056 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
4061 * pci_release_region - Release a PCI bar
4066 * Releases the PCI I/O and memory resources previously reserved by a
4070 void pci_release_region(struct pci_dev *pdev, int bar) in pci_release_region()
4085 dr->region_mask &= ~(1 << bar); in pci_release_region()
4090 * __pci_request_region - Reserved PCI I/O and memory resource
4108 static int __pci_request_region(struct pci_dev *pdev, int bar, in __pci_request_region()
4109 const char *res_name, int exclusive) in __pci_request_region()
4129 dr->region_mask |= 1 << bar; in __pci_request_region()
4135 &pdev->resource[bar]); in __pci_request_region()
4136 return -EBUSY; in __pci_request_region()
4140 * pci_request_region - Reserve PCI I/O and memory resource
4153 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) in pci_request_region()
4160 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4164 * Release selected PCI I/O and memory resources previously reserved.
4167 void pci_release_selected_regions(struct pci_dev *pdev, int bars) in pci_release_selected_regions()
4169 int i; in pci_release_selected_regions()
4177 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, in __pci_request_selected_regions()
4178 const char *res_name, int excl) in __pci_request_selected_regions()
4180 int i; in __pci_request_selected_regions()
4189 while (--i >= 0) in __pci_request_selected_regions()
4193 return -EBUSY; in __pci_request_selected_regions()
4198 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4203 int pci_request_selected_regions(struct pci_dev *pdev, int bars, in pci_request_selected_regions()
4210 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, in pci_request_selected_regions_exclusive()
4219 * pci_release_regions - Release reserved PCI I/O and memory resources
4223 * Releases all PCI I/O and memory resources previously reserved by a
4230 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4235 * pci_request_regions - Reserve PCI I/O and memory resources
4247 int pci_request_regions(struct pci_dev *pdev, const char *res_name) in pci_request_regions()
4250 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4255 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4264 * and the sysfs MMIO access will not be allowed.
4269 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) in pci_request_regions_exclusive()
4272 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4280 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, in pci_register_io_range()
4283 int ret = 0; in pci_register_io_range()
4288 return -EINVAL; in pci_register_io_range()
4292 return -ENOMEM; in pci_register_io_range()
4294 range->fwnode = fwnode; in pci_register_io_range()
4295 range->size = size; in pci_register_io_range()
4296 range->hw_start = addr; in pci_register_io_range()
4297 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4304 if (ret == -EEXIST) in pci_register_io_range()
4328 return (unsigned long)-1; in pci_address_to_pio()
4335 * pci_remap_iospace - Remap the memory mapped I/O space
4339 * Remap the memory mapped I/O space described by the @res and the CPU
4341 * architectures that have memory mapped IO functions defined (and the
4345 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) in pci_remap_iospace()
4348 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4350 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4351 return -EINVAL; in pci_remap_iospace()
4353 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4354 return -EINVAL; in pci_remap_iospace()
4364 return -ENODEV; in pci_remap_iospace()
4371 * pci_unmap_iospace - Unmap the memory mapped I/O space
4375 * architectures that have memory mapped IO functions defined (and the
4381 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4396 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4404 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, in devm_pci_remap_iospace()
4408 int error; in devm_pci_remap_iospace()
4412 return -ENOMEM; in devm_pci_remap_iospace()
4427 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4457 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4462 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4465 * All operations are managed and will be undone on driver detach.
4471 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4486 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4491 if (res->name) in devm_pci_remap_cfg_resource()
4493 res->name); in devm_pci_remap_cfg_resource()
4497 return IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4499 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4501 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4504 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4507 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4508 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4529 dev->is_busmaster = enable; in __pci_set_master()
4533 * pcibios_setup - process "pci=" kernel boot arguments
4545 * pcibios_set_master - enable PCI bus-mastering for device dev
4548 * Enables PCI bus-mastering for the device. This is the default
4572 * pci_set_master - enables bus-mastering for device dev
4575 * Enables bus-mastering on the device and calls pcibios_set_master()
4586 * pci_clear_master - disables bus-mastering for device dev
4596 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4601 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4603 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4605 int pci_set_cacheline_size(struct pci_dev *dev) in pci_set_cacheline_size()
4610 return -EINVAL; in pci_set_cacheline_size()
4629 return -EINVAL; in pci_set_cacheline_size()
4634 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4637 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4639 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4641 int pci_set_mwi(struct pci_dev *dev) in pci_set_mwi()
4646 int rc; in pci_set_mwi()
4655 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4665 * pcim_set_mwi - a device-managed pci_set_mwi()
4670 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4672 int pcim_set_mwi(struct pci_dev *dev) in pcim_set_mwi()
4678 return -ENOMEM; in pcim_set_mwi()
4680 dr->mwi = 1; in pcim_set_mwi()
4686 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4689 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4692 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4694 int pci_try_set_mwi(struct pci_dev *dev) in pci_try_set_mwi()
4705 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4708 * Disables PCI Memory-Write-Invalidate transaction on the device
4725 * pci_disable_parity - disable parity checking for device
4742 * pci_intx - enables/disables PCI INTx for device dev
4748 void pci_intx(struct pci_dev *pdev, int enable) in pci_intx()
4765 if (dr && !dr->restore_intx) { in pci_intx()
4766 dr->restore_intx = 1; in pci_intx()
4767 dr->orig_intx = !enable; in pci_intx()
4775 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4783 * We do a single dword read to retrieve both command and status. in pci_check_and_set_intx_mask()
4791 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4810 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4819 * pci_check_and_mask_intx - mask INTx on pending interrupt
4822 * Check if the device dev has its INTx line asserted, mask it and return
4832 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4835 * Check if the device dev has its INTx line asserted, unmask it if not and
4836 * return true. False is returned and the mask remains active if there was
4846 * pci_wait_for_pending_transaction - wait for pending transaction
4851 int pci_wait_for_pending_transaction(struct pci_dev *dev) in pci_wait_for_pending_transaction()
4862 * pcie_flr - initiate a PCIe function level reset
4866 * checking any flags and DEVCAP
4868 int pcie_flr(struct pci_dev *dev) in pcie_flr()
4875 if (dev->imm_ready) in pcie_flr()
4890 * pcie_reset_flr - initiate a PCIe function level reset
4896 int pcie_reset_flr(struct pci_dev *dev, bool probe) in pcie_reset_flr()
4898 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4899 return -ENOTTY; in pcie_reset_flr()
4901 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4902 return -ENOTTY; in pcie_reset_flr()
4911 static int pci_af_flr(struct pci_dev *dev, bool probe) in pci_af_flr()
4913 int pos; in pci_af_flr()
4918 return -ENOTTY; in pci_af_flr()
4920 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4921 return -ENOTTY; in pci_af_flr()
4925 return -ENOTTY; in pci_af_flr()
4931 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4932 * is used, so we use the control offset rather than status and shift in pci_af_flr()
4941 if (dev->imm_ready) in pci_af_flr()
4956 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4960 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4962 * PCI_D0. If that's the case and the device is not in a low-power state
4963 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4966 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4970 static int pci_pm_reset(struct pci_dev *dev, bool probe) in pci_pm_reset()
4974 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4975 return -ENOTTY; in pci_pm_reset()
4977 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4979 return -ENOTTY; in pci_pm_reset()
4984 if (dev->current_state != PCI_D0) in pci_pm_reset()
4985 return -EINVAL; in pci_pm_reset()
4989 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4994 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4997 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
5001 * pcie_wait_for_link_status - Wait for link status change
5006 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
5009 static int pcie_wait_for_link_status(struct pci_dev *pdev, in pcie_wait_for_link_status()
5027 return -ETIMEDOUT; in pcie_wait_for_link_status()
5031 * pcie_retrain_link - Request a link retrain and wait for it to complete
5039 * Return 0 if successful, or -ETIMEDOUT if training has not completed
5042 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt) in pcie_retrain_link()
5044 int rc; in pcie_retrain_link()
5057 if (pdev->clear_retrain_link) { in pcie_retrain_link()
5070 * pcie_wait_for_link_delay - Wait until link is active or inactive
5078 int delay) in pcie_wait_for_link_delay()
5080 int rc; in pcie_wait_for_link_delay()
5086 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
5120 * pcie_wait_for_link - Wait until link is active or inactive
5133 * spec says 100 ms, but firmware can lower it and we allow drivers to
5138 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) in pci_bus_max_d3cold_delay()
5141 int min_delay = 100; in pci_bus_max_d3cold_delay()
5142 int max_delay = 0; in pci_bus_max_d3cold_delay()
5144 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
5145 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
5146 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5147 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
5148 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5155 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5157 * @reset_type: reset type in human-readable form
5167 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5170 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) in pci_bridge_wait_for_secondary_bus()
5173 int delay; in pci_bridge_wait_for_secondary_bus()
5185 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
5189 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
5195 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
5201 child = list_first_entry(&dev->subordinate->devices, struct pci_dev, in pci_bridge_wait_for_secondary_bus()
5206 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
5216 * For PCIe downstream and root ports that do not support speeds in pci_bridge_wait_for_secondary_bus()
5221 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
5227 * Therefore we wait for 100 ms and check for the device presence in pci_bridge_wait_for_secondary_bus()
5239 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
5244 * whether the link is active and if not bail out early with in pci_bridge_wait_for_secondary_bus()
5247 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
5248 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5252 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5255 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
5263 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5267 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
5294 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5298 * Devices on the secondary bus are left in power-on state.
5300 int pci_bridge_secondary_bus_reset(struct pci_dev *dev) in pci_bridge_secondary_bus_reset()
5308 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe) in pci_parent_bus_reset()
5312 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5313 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5314 return -ENOTTY; in pci_parent_bus_reset()
5316 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5318 return -ENOTTY; in pci_parent_bus_reset()
5323 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5326 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe) in pci_reset_hotplug_slot()
5328 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5330 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5333 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5334 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5336 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5341 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) in pci_dev_reset_slot_function()
5343 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5344 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5345 return -ENOTTY; in pci_dev_reset_slot_function()
5347 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5350 static int pci_reset_bus_function(struct pci_dev *dev, bool probe) in pci_reset_bus_function()
5352 int rc; in pci_reset_bus_function()
5355 if (rc != -ENOTTY) in pci_reset_bus_function()
5363 device_lock(&dev->dev); in pci_dev_lock()
5369 int pci_dev_trylock(struct pci_dev *dev) in pci_dev_trylock()
5371 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5374 device_unlock(&dev->dev); in pci_dev_trylock()
5384 device_unlock(&dev->dev); in pci_dev_unlock()
5391 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5394 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5395 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5398 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5399 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5402 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5403 * reset and a simple register restore doesn't reliably return in pci_dev_save_and_disable()
5404 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5411 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5413 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5414 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5422 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5427 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5428 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5431 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5432 err_handler->reset_done(dev); in pci_dev_restore()
5435 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5451 int i, m; in reset_method_show()
5454 m = pdev->reset_methods[i]; in reset_method_show()
5468 static int reset_method_lookup(const char *name) in reset_method_lookup()
5470 int m; in reset_method_lookup()
5486 int m, n; in reset_method_store()
5490 pdev->reset_methods[0] = 0; in reset_method_store()
5502 return -ENOMEM; in reset_method_store()
5522 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5532 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5535 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5536 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5543 return -EINVAL; in reset_method_store()
5553 struct attribute *a, int n) in pci_dev_reset_method_attr_is_visible()
5560 return a->mode; in pci_dev_reset_method_attr_is_visible()
5569 * __pci_reset_function_locked - reset a PCI device function while holding
5577 * The device function is presumed to be unused and the caller is holding
5582 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5588 int __pci_reset_function_locked(struct pci_dev *dev) in __pci_reset_function_locked()
5590 int i, m, rc; in __pci_reset_function_locked()
5595 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5603 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5605 return -ENOTTY; in __pci_reset_function_locked()
5610 if (rc != -ENOTTY) in __pci_reset_function_locked()
5614 return -ENOTTY; in __pci_reset_function_locked()
5619 * pci_init_reset_methods - check whether device can be safely reset
5620 * and store supported reset mechanisms.
5624 * other functions in the same device. The PCI device must be in D0-D3hot
5627 * Stores reset mechanisms supported by device in reset_methods byte array
5632 int m, i, rc; in pci_init_reset_methods()
5642 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5643 else if (rc != -ENOTTY) in pci_init_reset_methods()
5647 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5651 * pci_reset_function - quiesce and reset a PCI device function
5660 * from __pci_reset_function_locked() in that it saves and restores device state
5661 * over the reset and takes the PCI device lock.
5666 int pci_reset_function(struct pci_dev *dev) in pci_reset_function()
5668 int rc; in pci_reset_function()
5671 return -ENOTTY; in pci_reset_function()
5686 * pci_reset_function_locked - quiesce and reset a PCI device function
5695 * from __pci_reset_function_locked() in that it saves and restores device state
5702 int pci_reset_function_locked(struct pci_dev *dev) in pci_reset_function_locked()
5704 int rc; in pci_reset_function_locked()
5707 return -ENOTTY; in pci_reset_function_locked()
5720 * pci_try_reset_function - quiesce and reset a PCI device function
5723 * Same as above, except return -EAGAIN if unable to lock device.
5725 int pci_try_reset_function(struct pci_dev *dev) in pci_try_reset_function()
5727 int rc; in pci_try_reset_function()
5730 return -ENOTTY; in pci_try_reset_function()
5733 return -EAGAIN; in pci_try_reset_function()
5750 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5753 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5754 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5755 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5767 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5769 if (dev->subordinate) in pci_bus_lock()
5770 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5779 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5780 if (dev->subordinate) in pci_bus_unlock()
5781 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5787 static int pci_bus_trylock(struct pci_bus *bus) in pci_bus_trylock()
5791 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5794 if (dev->subordinate) { in pci_bus_trylock()
5795 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
5804 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5805 if (dev->subordinate) in pci_bus_trylock()
5806 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5817 if (slot->bus->self && in pci_slot_resettable()
5818 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5821 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5822 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5824 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5825 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5837 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5838 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5841 if (dev->subordinate) in pci_slot_lock()
5842 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5851 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5852 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5854 if (dev->subordinate) in pci_slot_unlock()
5855 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5861 static int pci_slot_trylock(struct pci_slot *slot) in pci_slot_trylock()
5865 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5866 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5870 if (dev->subordinate) { in pci_slot_trylock()
5871 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5881 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5882 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5884 if (dev->subordinate) in pci_slot_trylock()
5885 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5892 * Save and disable devices from the top of the tree down while holding
5899 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5901 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5902 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5915 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5917 if (dev->subordinate) in pci_bus_restore_locked()
5918 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5923 * Save and disable devices from the top of the tree down while holding
5930 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5931 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5934 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5935 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5948 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5949 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5952 if (dev->subordinate) in pci_slot_restore_locked()
5953 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5957 static int pci_slot_reset(struct pci_slot *slot, bool probe) in pci_slot_reset()
5959 int rc; in pci_slot_reset()
5962 return -ENOTTY; in pci_slot_reset()
5969 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5978 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5983 int pci_probe_reset_slot(struct pci_slot *slot) in pci_probe_reset_slot()
5990 * __pci_reset_slot - Try to reset a PCI slot
5998 * function of the slot and any subordinate buses behind the slot are reset
5999 * through this function. PCI config space of all devices in the slot and
6000 * behind the slot is saved before and restored after reset.
6002 * Same as above except return -EAGAIN if the slot cannot be locked
6004 static int __pci_reset_slot(struct pci_slot *slot) in __pci_reset_slot()
6006 int rc; in __pci_reset_slot()
6015 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
6019 rc = -EAGAIN; in __pci_reset_slot()
6024 static int pci_bus_reset(struct pci_bus *bus, bool probe) in pci_bus_reset()
6026 int ret; in pci_bus_reset()
6028 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
6029 return -ENOTTY; in pci_bus_reset()
6038 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
6046 * pci_bus_error_reset - reset the bridge's subordinate bus
6053 int pci_bus_error_reset(struct pci_dev *bridge) in pci_bus_error_reset()
6055 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
6059 return -ENOTTY; in pci_bus_error_reset()
6062 if (list_empty(&bus->slots)) in pci_bus_error_reset()
6065 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
6069 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
6077 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
6081 * pci_probe_reset_bus - probe whether a PCI bus can be reset
6086 int pci_probe_reset_bus(struct pci_bus *bus) in pci_probe_reset_bus()
6093 * __pci_reset_bus - Try to reset a PCI bus
6096 * Same as above except return -EAGAIN if the bus cannot be locked
6098 static int __pci_reset_bus(struct pci_bus *bus) in __pci_reset_bus()
6100 int rc; in __pci_reset_bus()
6109 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
6113 rc = -EAGAIN; in __pci_reset_bus()
6119 * pci_reset_bus - Try to reset a PCI bus
6122 * Same as above except return -EAGAIN if the bus cannot be locked
6124 int pci_reset_bus(struct pci_dev *pdev) in pci_reset_bus()
6126 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
6127 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
6132 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6138 int pcix_get_max_mmrbc(struct pci_dev *dev) in pcix_get_max_mmrbc()
6140 int cap; in pcix_get_max_mmrbc()
6145 return -EINVAL; in pcix_get_max_mmrbc()
6148 return -EINVAL; in pcix_get_max_mmrbc()
6155 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6161 int pcix_get_mmrbc(struct pci_dev *dev) in pcix_get_mmrbc()
6163 int cap; in pcix_get_mmrbc()
6168 return -EINVAL; in pcix_get_mmrbc()
6171 return -EINVAL; in pcix_get_mmrbc()
6178 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6181 * valid values are 512, 1024, 2048, 4096
6186 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) in pcix_set_mmrbc()
6188 int cap; in pcix_set_mmrbc()
6193 return -EINVAL; in pcix_set_mmrbc()
6195 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
6199 return -EINVAL; in pcix_set_mmrbc()
6202 return -EINVAL; in pcix_set_mmrbc()
6205 return -E2BIG; in pcix_set_mmrbc()
6208 return -EINVAL; in pcix_set_mmrbc()
6212 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
6213 return -EIO; in pcix_set_mmrbc()
6218 return -EIO; in pcix_set_mmrbc()
6225 * pcie_get_readrq - get PCI Express read request size
6230 int pcie_get_readrq(struct pci_dev *dev) in pcie_get_readrq()
6241 * pcie_set_readrq - set PCI Express maximum memory read request
6244 * valid values are 128, 256, 512, 1024, 2048, 4096
6248 int pcie_set_readrq(struct pci_dev *dev, int rq) in pcie_set_readrq()
6251 int ret; in pcie_set_readrq()
6252 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
6255 return -EINVAL; in pcie_set_readrq()
6263 int mps = pcie_get_mps(dev); in pcie_set_readrq()
6269 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8); in pcie_set_readrq()
6271 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
6272 int max_mrrs = pcie_get_readrq(dev); in pcie_set_readrq()
6276 return -EINVAL; in pcie_set_readrq()
6288 * pcie_get_mps - get PCI Express maximum payload size
6293 int pcie_get_mps(struct pci_dev *dev) in pcie_get_mps()
6304 * pcie_set_mps - set PCI Express maximum payload size
6307 * valid values are 128, 256, 512, 1024, 2048, 4096
6311 int pcie_set_mps(struct pci_dev *dev, int mps) in pcie_set_mps()
6314 int ret; in pcie_set_mps()
6317 return -EINVAL; in pcie_set_mps()
6319 v = ffs(mps) - 8; in pcie_set_mps()
6320 if (v > dev->pcie_mpss) in pcie_set_mps()
6321 return -EINVAL; in pcie_set_mps()
6336 int pcie_link_speed_mbps(struct pci_dev *pdev) in pcie_link_speed_mbps()
6339 int err; in pcie_link_speed_mbps()
6362 return -EINVAL; in pcie_link_speed_mbps()
6367 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6368 * device and its bandwidth limitation
6374 * Walk up the PCI device chain and find the point where the minimum
6375 * bandwidth is available. Return the bandwidth available there and (if
6376 * limiting_dev, speed, and width pointers are supplied) information about
6424 * pcie_get_speed_cap - query for the PCI device's link speed capability
6441 * where only 2.5 GT/s and 5.0 GT/s speeds were defined. in pcie_get_speed_cap()
6445 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6460 * pcie_get_width_cap - query for the PCI device's link width capability
6479 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6485 * and width, multiplying them, and applying encoding overhead. The result
6501 * __pcie_print_link_status - Report the PCI device's link speed and width
6506 * capable of, report the device's maximum possible bandwidth and the
6508 * the available bandwidth, even if the device isn't constrained.
6534 * pcie_print_link_status - Report the PCI device's link speed and width
6546 * pci_select_bars - Make BAR mask from the type of resource
6552 int pci_select_bars(struct pci_dev *dev, unsigned long flags) in pci_select_bars()
6554 int i, bars = 0; in pci_select_bars()
6570 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, in pci_set_vga_state_arch()
6571 unsigned int command_bits, u32 flags) in pci_set_vga_state_arch()
6580 * pci_set_vga_state - set VGA decode state on device and parents if requested
6583 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6584 * @flags: traverse ancestors and change bridges
6587 int pci_set_vga_state(struct pci_dev *dev, bool decode, in pci_set_vga_state()
6588 unsigned int command_bits, u32 flags) in pci_set_vga_state()
6593 int rc; in pci_set_vga_state()
6614 bus = dev->bus; in pci_set_vga_state()
6616 bridge = bus->self; in pci_set_vga_state()
6627 bus = bus->parent; in pci_set_vga_state()
6640 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6644 return adev->power.flags.power_resources && in pci_pr3_present()
6645 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6651 * pci_add_dma_alias - Add a DMA devfn alias for a device
6653 * @devfn_from: alias slot and function
6656 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6657 * which is used to program permissible bus-devfn source addresses for DMA
6659 * and are useful for devices generating DMA requests beyond or different
6660 * from their logical bus-devfn. Examples include device quirks where the
6661 * device simply uses the wrong devfn, as well as non-transparent bridges
6665 * prior to any potential DMA mapping and therefore prior to driver probing
6671 unsigned int nr_devfns) in pci_add_dma_alias()
6673 int devfn_to; in pci_add_dma_alias()
6675 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6676 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6678 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6679 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6680 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6685 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6698 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6699 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6700 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6701 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6714 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6720 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6722 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6725 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6730 * pci_real_dma_dev - Get PCI DMA device for PCI device
6733 * Permits the platform to provide architecture-specific functionality to
6750 * Arches that don't want to expose struct resource to userland as-is in
6751 * sysfs and /proc can implement their own pci_resource_to_user().
6753 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, in pci_resource_to_user()
6757 *start = rsrc->start; in pci_resource_to_user()
6758 *end = rsrc->end; in pci_resource_to_user()
6765 * pci_specified_resource_alignment - get resource alignment specified by user.
6775 int align_order, count; in pci_specified_resource_alignment()
6778 int ret; in pci_specified_resource_alignment()
6826 static void pci_request_resource_alignment(struct pci_dev *dev, int bar, in pci_request_resource_alignment()
6829 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6833 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6836 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6862 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and in pci_request_resource_alignment()
6863 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6869 * the "pci=resource_alignment" argument, "resize" is true and we in pci_request_resource_alignment()
6871 * devices and we use the second. in pci_request_resource_alignment()
6878 r->start = 0; in pci_request_resource_alignment()
6879 r->end = align - 1; in pci_request_resource_alignment()
6881 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6882 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6883 r->start = align; in pci_request_resource_alignment()
6884 r->end = r->start + size - 1; in pci_request_resource_alignment()
6886 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6890 * This function disables memory decoding and releases memory resources
6893 * Later on, the kernel will assign page-aligned memory resource back
6898 int i; in pci_reassigndev_resource_alignment()
6905 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6907 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6910 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6918 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6919 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6936 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6938 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6939 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6941 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6942 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6943 r->start = 0; in pci_reassigndev_resource_alignment()
6966 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6967 return -EINVAL; in resource_alignment_store()
6971 return -ENOMEM; in resource_alignment_store()
6994 static int __init pci_resource_alignment_sysfs_init(void) in pci_resource_alignment_sysfs_init()
7015 int domain_nr; in of_pci_reserve_static_domain_nr()
7030 static int of_pci_bus_find_domain_nr(struct device *parent) in of_pci_bus_find_domain_nr()
7033 int domain_nr; in of_pci_bus_find_domain_nr()
7047 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
7065 if (bus->domain_nr < 0) in of_pci_bus_release_domain_nr()
7069 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr) in of_pci_bus_release_domain_nr()
7070 ida_free(&pci_domain_nr_static_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
7072 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
7075 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) in pci_bus_find_domain_nr()
7090 * pci_ext_cfg_avail - can we access extended PCI config space?
7096 int __weak pci_ext_cfg_avail(void) in pci_ext_cfg_avail()
7106 static int __init pci_setup(char *str) in pci_setup()
7175 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
7179 * service available during an early_param() call. So we allocate memory and
7180 * copy the variable here before the init section is freed.
7183 static int __init pci_realloc_setup_params(void) in pci_realloc_setup_params()