pci/controller/pcie-xilinx-nwl.c

3  * PCIe host controller driver for NWL PCIe Bridge
4  * Based on pcie-xilinx.c, pci-tegra.c
161 	phys_addr_t phys_pcie_reg_base;	/* Physical PCIe Controller Base */
174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)  in nwl_bridge_readl()  argument
176 	return readl(pcie->breg_base + off);  in nwl_bridge_readl()
179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)  in nwl_bridge_writel()  argument
181 	writel(val, pcie->breg_base + off);  in nwl_bridge_writel()
184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)  in nwl_pcie_link_up()  argument
186 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)  in nwl_pcie_link_up()
191 static bool nwl_phy_link_up(struct nwl_pcie *pcie)  in nwl_phy_link_up()  argument
193 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)  in nwl_phy_link_up()
198 static int nwl_wait_for_link(struct nwl_pcie *pcie)  in nwl_wait_for_link()  argument
200 	struct device *dev = pcie->dev;  in nwl_wait_for_link()
205 		if (nwl_phy_link_up(pcie))  in nwl_wait_for_link()
216 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_valid_device()  local
220 		if (!nwl_pcie_link_up(pcie))  in nwl_pcie_valid_device()
242 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_map_bus()  local
247 	return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);  in nwl_pcie_map_bus()
250 /* PCIe operations */
259 	struct nwl_pcie *pcie = data;  in nwl_pcie_misc_handler()  local
260 	struct device *dev = pcie->dev;  in nwl_pcie_misc_handler()
264 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_misc_handler()
309 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);  in nwl_pcie_misc_handler()
317 	struct nwl_pcie *pcie;  in nwl_pcie_leg_handler()  local
322 	pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_leg_handler()
324 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_leg_handler()
327 			generic_handle_domain_irq(pcie->intx_irq_domain, bit);  in nwl_pcie_leg_handler()
333 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)  in nwl_pcie_handle_msi_irq()  argument
335 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_handle_msi_irq()
339 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {  in nwl_pcie_handle_msi_irq()
341 			nwl_bridge_writel(pcie, 1 << bit, status_reg);  in nwl_pcie_handle_msi_irq()
350 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_high()  local
353 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);  in nwl_pcie_msi_handler_high()
360 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_low()  local
363 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);  in nwl_pcie_msi_handler_low()
369 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_mask_intx_irq()  local
375 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_mask_intx_irq()
376 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_mask_intx_irq()
377 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);  in nwl_mask_intx_irq()
378 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_mask_intx_irq()
383 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_unmask_intx_irq()  local
389 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_unmask_intx_irq()
390 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_unmask_intx_irq()
391 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);  in nwl_unmask_intx_irq()
392 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_unmask_intx_irq()
436 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_compose_msi_msg()  local
437 	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;  in nwl_compose_msi_msg()
459 	struct nwl_pcie *pcie = domain->host_data;  in nwl_irq_domain_alloc()  local
460 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_alloc()
485 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_irq_domain_free()  local
486 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_free()
499 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_msi_irq_domain()  argument
502 	struct device *dev = pcie->dev;  in nwl_pcie_init_msi_irq_domain()
504 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_init_msi_irq_domain()
507 						&dev_msi_domain_ops, pcie);  in nwl_pcie_init_msi_irq_domain()
524 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_irq_domain()  argument
526 	struct device *dev = pcie->dev;  in nwl_pcie_init_irq_domain()
536 	pcie->intx_irq_domain = irq_domain_add_linear(intc_node,  in nwl_pcie_init_irq_domain()
539 						      pcie);  in nwl_pcie_init_irq_domain()
541 	if (!pcie->intx_irq_domain) {  in nwl_pcie_init_irq_domain()
546 	raw_spin_lock_init(&pcie->leg_mask_lock);  in nwl_pcie_init_irq_domain()
547 	nwl_pcie_init_msi_irq_domain(pcie);  in nwl_pcie_init_irq_domain()
551 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)  in nwl_pcie_enable_msi()  argument
553 	struct device *dev = pcie->dev;  in nwl_pcie_enable_msi()
555 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_enable_msi()
567 					 nwl_pcie_msi_handler_high, pcie);  in nwl_pcie_enable_msi()
575 					 nwl_pcie_msi_handler_low, pcie);  in nwl_pcie_enable_msi()
578 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;  in nwl_pcie_enable_msi()
585 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
589 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
593 	base = pcie->phys_pcie_reg_base;  in nwl_pcie_enable_msi()
594 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);  in nwl_pcie_enable_msi()
595 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);  in nwl_pcie_enable_msi()
601 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
603 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &  in nwl_pcie_enable_msi()
606 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
612 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
614 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &  in nwl_pcie_enable_msi()
617 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
622 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)  in nwl_pcie_bridge_init()  argument
624 	struct device *dev = pcie->dev;  in nwl_pcie_bridge_init()
629 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;  in nwl_pcie_bridge_init()
636 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
638 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
642 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,  in nwl_pcie_bridge_init()
646 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |  in nwl_pcie_bridge_init()
650 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);  in nwl_pcie_bridge_init()
653 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,  in nwl_pcie_bridge_init()
656 	/* This routes the PCIe DMA traffic to go through CCI path */  in nwl_pcie_bridge_init()
658 		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |  in nwl_pcie_bridge_init()
661 	err = nwl_wait_for_link(pcie);  in nwl_pcie_bridge_init()
665 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;  in nwl_pcie_bridge_init()
672 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
675 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
679 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
681 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
684 	if (nwl_pcie_link_up(pcie))  in nwl_pcie_bridge_init()
690 	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");  in nwl_pcie_bridge_init()
691 	if (pcie->irq_misc < 0)  in nwl_pcie_bridge_init()
694 	err = devm_request_irq(dev, pcie->irq_misc,  in nwl_pcie_bridge_init()
696 			       "nwl_pcie:misc", pcie);  in nwl_pcie_bridge_init()
699 			pcie->irq_misc);  in nwl_pcie_bridge_init()
704 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
707 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_bridge_init()
711 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
714 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
717 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_bridge_init()
721 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
724 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |  in nwl_pcie_bridge_init()
730 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,  in nwl_pcie_parse_dt()  argument
733 	struct device *dev = pcie->dev;  in nwl_pcie_parse_dt()
737 	pcie->breg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
738 	if (IS_ERR(pcie->breg_base))  in nwl_pcie_parse_dt()
739 		return PTR_ERR(pcie->breg_base);  in nwl_pcie_parse_dt()
740 	pcie->phys_breg_base = res->start;  in nwl_pcie_parse_dt()
743 	pcie->pcireg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
744 	if (IS_ERR(pcie->pcireg_base))  in nwl_pcie_parse_dt()
745 		return PTR_ERR(pcie->pcireg_base);  in nwl_pcie_parse_dt()
746 	pcie->phys_pcie_reg_base = res->start;  in nwl_pcie_parse_dt()
749 	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);  in nwl_pcie_parse_dt()
750 	if (IS_ERR(pcie->ecam_base))  in nwl_pcie_parse_dt()
751 		return PTR_ERR(pcie->ecam_base);  in nwl_pcie_parse_dt()
752 	pcie->phys_ecam_base = res->start;  in nwl_pcie_parse_dt()
755 	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");  in nwl_pcie_parse_dt()
756 	if (pcie->irq_intx < 0)  in nwl_pcie_parse_dt()
757 		return pcie->irq_intx;  in nwl_pcie_parse_dt()
759 	irq_set_chained_handler_and_data(pcie->irq_intx,  in nwl_pcie_parse_dt()
760 					 nwl_pcie_leg_handler, pcie);  in nwl_pcie_parse_dt()
766 	{ .compatible = "xlnx,nwl-pcie-2.11", },
773 	struct nwl_pcie *pcie;  in nwl_pcie_probe()  local
777 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in nwl_pcie_probe()
781 	pcie = pci_host_bridge_priv(bridge);  in nwl_pcie_probe()
783 	pcie->dev = dev;  in nwl_pcie_probe()
785 	err = nwl_pcie_parse_dt(pcie, pdev);  in nwl_pcie_probe()
791 	pcie->clk = devm_clk_get(dev, NULL);  in nwl_pcie_probe()
792 	if (IS_ERR(pcie->clk))  in nwl_pcie_probe()
793 		return PTR_ERR(pcie->clk);  in nwl_pcie_probe()
795 	err = clk_prepare_enable(pcie->clk);  in nwl_pcie_probe()
797 		dev_err(dev, "can't enable PCIe ref clock\n");  in nwl_pcie_probe()
801 	err = nwl_pcie_bridge_init(pcie);  in nwl_pcie_probe()
807 	err = nwl_pcie_init_irq_domain(pcie);  in nwl_pcie_probe()
813 	bridge->sysdata = pcie;  in nwl_pcie_probe()
817 		err = nwl_pcie_enable_msi(pcie);  in nwl_pcie_probe()
829 		.name = "nwl-pcie",