Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
33 /* Egress - Bridge translation registers */
43 /* Ingress - address translations */
51 /* Rxed msg fifo - Interrupt status registers */
176 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 struct device *dev = pcie->dev; in nwl_wait_for_link()
211 return -ETIMEDOUT; in nwl_wait_for_link()
216 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
230 * nwl_pcie_map_bus - Get configuration base
242 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
247 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
260 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
288 dev_err(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
297 dev_err(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
327 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in nwl_pcie_leg_handler()
335 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
342 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
374 mask = 1 << (data->hwirq - 1); in nwl_mask_intx_irq()
375 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
378 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
388 mask = 1 << (data->hwirq - 1); in nwl_unmask_intx_irq()
389 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
392 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
407 irq_set_chip_data(irq, domain->host_data); in nwl_intx_map()
437 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
439 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
440 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
441 msg->data = data->hwirq; in nwl_compose_msi_msg()
447 return -EINVAL; in nwl_msi_set_affinity()
459 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
460 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
464 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
465 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
468 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
469 return -ENOSPC; in nwl_irq_domain_alloc()
474 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
477 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
486 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
488 mutex_lock(&msi->lock); in nwl_irq_domain_free()
489 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
491 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
502 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
503 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
504 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
506 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
508 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
510 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
512 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
514 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
515 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
517 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
518 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
526 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
527 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
533 return -EINVAL; in nwl_pcie_init_irq_domain()
536 pcie->intx_irq_domain = irq_domain_add_linear(intc_node, in nwl_pcie_init_irq_domain()
541 if (!pcie->intx_irq_domain) { in nwl_pcie_init_irq_domain()
543 return -ENOMEM; in nwl_pcie_init_irq_domain()
546 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
553 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
555 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
559 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
562 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
563 if (msi->irq_msi1 < 0) in nwl_pcie_enable_msi()
564 return -EINVAL; in nwl_pcie_enable_msi()
566 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
570 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
571 if (msi->irq_msi0 < 0) in nwl_pcie_enable_msi()
572 return -EINVAL; in nwl_pcie_enable_msi()
574 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
581 return -EIO; in nwl_pcie_enable_msi()
593 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
624 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
636 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
638 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
657 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
667 dev_err(dev, "ECAM is not present\n"); in nwl_pcie_bridge_init()
671 /* Enable ECAM */ in nwl_pcie_bridge_init()
679 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
681 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
690 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
691 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
692 return -EINVAL; in nwl_pcie_bridge_init()
694 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
699 pcie->irq_misc); in nwl_pcie_bridge_init()
733 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
737 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
738 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
739 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
740 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
743 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
744 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
745 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
746 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
749 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
750 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
751 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
752 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
755 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
756 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
757 return pcie->irq_intx; in nwl_pcie_parse_dt()
759 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
766 { .compatible = "xlnx,nwl-pcie-2.11", },
772 struct device *dev = &pdev->dev; in nwl_pcie_probe()
779 return -ENODEV; in nwl_pcie_probe()
783 pcie->dev = dev; in nwl_pcie_probe()
791 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
792 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
793 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
795 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
813 bridge->sysdata = pcie; in nwl_pcie_probe()
814 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
829 .name = "nwl-pcie",