Lines Matching full:pcie
3 * MediaTek PCIe host controller driver.
116 * struct mtk_gen3_pcie - PCIe port information
117 * @dev: pointer to PCIe device
123 * @clks: PCIe clocks
124 * @num_clks: PCIe clocks count for this port
125 * @irq: PCIe controller interrupt number
199 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
214 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
244 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, in mtk_pcie_set_trans_table() argument
268 dev_err(pcie->dev, "illegal table size %#llx\n", in mtk_pcie_set_trans_table()
273 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; in mtk_pcie_set_trans_table()
289 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", in mtk_pcie_set_trans_table()
300 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", in mtk_pcie_set_trans_table()
306 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) in mtk_pcie_enable_msi() argument
312 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_enable_msi()
314 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + in mtk_pcie_enable_msi()
316 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG + in mtk_pcie_enable_msi()
322 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + in mtk_pcie_enable_msi()
326 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); in mtk_pcie_enable_msi()
328 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); in mtk_pcie_enable_msi()
330 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_enable_msi()
332 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_enable_msi()
335 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) in mtk_pcie_startup_port() argument
338 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_startup_port()
344 val = readl_relaxed(pcie->base + PCIE_SETTING_REG); in mtk_pcie_startup_port()
346 writel_relaxed(val, pcie->base + PCIE_SETTING_REG); in mtk_pcie_startup_port()
349 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1); in mtk_pcie_startup_port()
352 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1); in mtk_pcie_startup_port()
355 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_startup_port()
357 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_startup_port()
360 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); in mtk_pcie_startup_port()
362 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); in mtk_pcie_startup_port()
365 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
367 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
370 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) in mtk_pcie_startup_port()
379 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
382 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, in mtk_pcie_startup_port()
389 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG); in mtk_pcie_startup_port()
393 dev_err(pcie->dev, in mtk_pcie_startup_port()
394 "PCIe link down, current LTSSM state: %s (%#x)\n", in mtk_pcie_startup_port()
399 mtk_pcie_enable_msi(pcie); in mtk_pcie_startup_port()
401 /* Set PCIe translation windows */ in mtk_pcie_startup_port()
418 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, in mtk_pcie_startup_port()
461 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_compose_msi_msg() local
469 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", in mtk_compose_msi_msg()
486 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_msi_bottom_irq_mask() local
492 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_mask()
496 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_mask()
502 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_msi_bottom_irq_unmask() local
508 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_unmask()
512 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_unmask()
528 struct mtk_gen3_pcie *pcie = domain->host_data; in mtk_msi_bottom_domain_alloc() local
532 mutex_lock(&pcie->lock); in mtk_msi_bottom_domain_alloc()
534 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM, in mtk_msi_bottom_domain_alloc()
537 mutex_unlock(&pcie->lock); in mtk_msi_bottom_domain_alloc()
543 msi_set = &pcie->msi_sets[set_idx]; in mtk_msi_bottom_domain_alloc()
556 struct mtk_gen3_pcie *pcie = domain->host_data; in mtk_msi_bottom_domain_free() local
559 mutex_lock(&pcie->lock); in mtk_msi_bottom_domain_free()
561 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, in mtk_msi_bottom_domain_free()
564 mutex_unlock(&pcie->lock); in mtk_msi_bottom_domain_free()
576 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_mask() local
580 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_intx_mask()
581 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_mask()
583 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_mask()
584 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_intx_mask()
589 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_unmask() local
593 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_intx_unmask()
594 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_unmask()
596 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_unmask()
597 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_intx_unmask()
610 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_eoi() local
614 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG); in mtk_intx_eoi()
638 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) in mtk_pcie_init_irq_domains() argument
640 struct device *dev = pcie->dev; in mtk_pcie_init_irq_domains()
644 raw_spin_lock_init(&pcie->irq_lock); in mtk_pcie_init_irq_domains()
653 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, in mtk_pcie_init_irq_domains()
654 &intx_domain_ops, pcie); in mtk_pcie_init_irq_domains()
655 if (!pcie->intx_domain) { in mtk_pcie_init_irq_domains()
662 mutex_init(&pcie->lock); in mtk_pcie_init_irq_domains()
664 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, in mtk_pcie_init_irq_domains()
665 &mtk_msi_bottom_domain_ops, pcie); in mtk_pcie_init_irq_domains()
666 if (!pcie->msi_bottom_domain) { in mtk_pcie_init_irq_domains()
672 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode, in mtk_pcie_init_irq_domains()
674 pcie->msi_bottom_domain); in mtk_pcie_init_irq_domains()
675 if (!pcie->msi_domain) { in mtk_pcie_init_irq_domains()
685 irq_domain_remove(pcie->msi_bottom_domain); in mtk_pcie_init_irq_domains()
687 irq_domain_remove(pcie->intx_domain); in mtk_pcie_init_irq_domains()
693 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_teardown() argument
695 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); in mtk_pcie_irq_teardown()
697 if (pcie->intx_domain) in mtk_pcie_irq_teardown()
698 irq_domain_remove(pcie->intx_domain); in mtk_pcie_irq_teardown()
700 if (pcie->msi_domain) in mtk_pcie_irq_teardown()
701 irq_domain_remove(pcie->msi_domain); in mtk_pcie_irq_teardown()
703 if (pcie->msi_bottom_domain) in mtk_pcie_irq_teardown()
704 irq_domain_remove(pcie->msi_bottom_domain); in mtk_pcie_irq_teardown()
706 irq_dispose_mapping(pcie->irq); in mtk_pcie_irq_teardown()
709 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx) in mtk_pcie_msi_handler() argument
711 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx]; in mtk_pcie_msi_handler()
726 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq); in mtk_pcie_msi_handler()
733 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc); in mtk_pcie_irq_handler() local
740 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG); in mtk_pcie_irq_handler()
743 generic_handle_domain_irq(pcie->intx_domain, in mtk_pcie_irq_handler()
749 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT); in mtk_pcie_irq_handler()
751 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG); in mtk_pcie_irq_handler()
757 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) in mtk_pcie_setup_irq() argument
759 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
763 err = mtk_pcie_init_irq_domains(pcie); in mtk_pcie_setup_irq()
767 pcie->irq = platform_get_irq(pdev, 0); in mtk_pcie_setup_irq()
768 if (pcie->irq < 0) in mtk_pcie_setup_irq()
769 return pcie->irq; in mtk_pcie_setup_irq()
771 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie); in mtk_pcie_setup_irq()
776 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) in mtk_pcie_parse_port() argument
778 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
783 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); in mtk_pcie_parse_port()
786 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_parse_port()
787 if (IS_ERR(pcie->base)) { in mtk_pcie_parse_port()
789 return PTR_ERR(pcie->base); in mtk_pcie_parse_port()
792 pcie->reg_base = regs->start; in mtk_pcie_parse_port()
794 pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy"); in mtk_pcie_parse_port()
795 if (IS_ERR(pcie->phy_reset)) { in mtk_pcie_parse_port()
796 ret = PTR_ERR(pcie->phy_reset); in mtk_pcie_parse_port()
803 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); in mtk_pcie_parse_port()
804 if (IS_ERR(pcie->mac_reset)) { in mtk_pcie_parse_port()
805 ret = PTR_ERR(pcie->mac_reset); in mtk_pcie_parse_port()
812 pcie->phy = devm_phy_optional_get(dev, "pcie-phy"); in mtk_pcie_parse_port()
813 if (IS_ERR(pcie->phy)) { in mtk_pcie_parse_port()
814 ret = PTR_ERR(pcie->phy); in mtk_pcie_parse_port()
821 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in mtk_pcie_parse_port()
822 if (pcie->num_clks < 0) { in mtk_pcie_parse_port()
824 return pcie->num_clks; in mtk_pcie_parse_port()
830 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) in mtk_pcie_power_up() argument
832 struct device *dev = pcie->dev; in mtk_pcie_power_up()
836 reset_control_deassert(pcie->phy_reset); in mtk_pcie_power_up()
838 err = phy_init(pcie->phy); in mtk_pcie_power_up()
844 err = phy_power_on(pcie->phy); in mtk_pcie_power_up()
851 reset_control_deassert(pcie->mac_reset); in mtk_pcie_power_up()
856 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); in mtk_pcie_power_up()
867 reset_control_assert(pcie->mac_reset); in mtk_pcie_power_up()
868 phy_power_off(pcie->phy); in mtk_pcie_power_up()
870 phy_exit(pcie->phy); in mtk_pcie_power_up()
872 reset_control_assert(pcie->phy_reset); in mtk_pcie_power_up()
877 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) in mtk_pcie_power_down() argument
879 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); in mtk_pcie_power_down()
881 pm_runtime_put_sync(pcie->dev); in mtk_pcie_power_down()
882 pm_runtime_disable(pcie->dev); in mtk_pcie_power_down()
883 reset_control_assert(pcie->mac_reset); in mtk_pcie_power_down()
885 phy_power_off(pcie->phy); in mtk_pcie_power_down()
886 phy_exit(pcie->phy); in mtk_pcie_power_down()
887 reset_control_assert(pcie->phy_reset); in mtk_pcie_power_down()
890 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) in mtk_pcie_setup() argument
894 err = mtk_pcie_parse_port(pcie); in mtk_pcie_setup()
902 reset_control_assert(pcie->phy_reset); in mtk_pcie_setup()
903 reset_control_assert(pcie->mac_reset); in mtk_pcie_setup()
907 err = mtk_pcie_power_up(pcie); in mtk_pcie_setup()
912 err = mtk_pcie_startup_port(pcie); in mtk_pcie_setup()
916 err = mtk_pcie_setup_irq(pcie); in mtk_pcie_setup()
923 mtk_pcie_power_down(pcie); in mtk_pcie_setup()
931 struct mtk_gen3_pcie *pcie; in mtk_pcie_probe() local
935 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in mtk_pcie_probe()
939 pcie = pci_host_bridge_priv(host); in mtk_pcie_probe()
941 pcie->dev = dev; in mtk_pcie_probe()
942 platform_set_drvdata(pdev, pcie); in mtk_pcie_probe()
944 err = mtk_pcie_setup(pcie); in mtk_pcie_probe()
949 host->sysdata = pcie; in mtk_pcie_probe()
953 mtk_pcie_irq_teardown(pcie); in mtk_pcie_probe()
954 mtk_pcie_power_down(pcie); in mtk_pcie_probe()
963 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev); in mtk_pcie_remove() local
964 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_remove()
971 mtk_pcie_irq_teardown(pcie); in mtk_pcie_remove()
972 mtk_pcie_power_down(pcie); in mtk_pcie_remove()
975 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_save() argument
979 raw_spin_lock(&pcie->irq_lock); in mtk_pcie_irq_save()
981 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_irq_save()
984 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_irq_save()
990 raw_spin_unlock(&pcie->irq_lock); in mtk_pcie_irq_save()
993 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_restore() argument
997 raw_spin_lock(&pcie->irq_lock); in mtk_pcie_irq_restore()
999 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_irq_restore()
1002 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_irq_restore()
1008 raw_spin_unlock(&pcie->irq_lock); in mtk_pcie_irq_restore()
1011 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie) in mtk_pcie_turn_off_link() argument
1015 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG); in mtk_pcie_turn_off_link()
1017 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG); in mtk_pcie_turn_off_link()
1020 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val, in mtk_pcie_turn_off_link()
1028 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_suspend_noirq() local
1033 err = mtk_pcie_turn_off_link(pcie); in mtk_pcie_suspend_noirq()
1035 dev_err(pcie->dev, "cannot enter L2 state\n"); in mtk_pcie_suspend_noirq()
1040 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_suspend_noirq()
1042 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_suspend_noirq()
1044 dev_dbg(pcie->dev, "entered L2 states successfully"); in mtk_pcie_suspend_noirq()
1046 mtk_pcie_irq_save(pcie); in mtk_pcie_suspend_noirq()
1047 mtk_pcie_power_down(pcie); in mtk_pcie_suspend_noirq()
1054 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_resume_noirq() local
1057 err = mtk_pcie_power_up(pcie); in mtk_pcie_resume_noirq()
1061 err = mtk_pcie_startup_port(pcie); in mtk_pcie_resume_noirq()
1063 mtk_pcie_power_down(pcie); in mtk_pcie_resume_noirq()
1067 mtk_pcie_irq_restore(pcie); in mtk_pcie_resume_noirq()
1078 { .compatible = "mediatek,mt8192-pcie" },
1087 .name = "mtk-pcie-gen3",