Lines Matching full:pcie
40 /* Broadcom STB PCIe Register Offsets */
153 /* PCIe parameters */
187 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
188 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
189 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
227 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
228 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
254 /* Internal PCIe Host Controller Information.*/
271 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
272 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
277 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
279 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
348 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
354 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
359 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
366 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
372 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
384 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
386 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
387 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
390 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
393 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
396 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
406 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
407 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
413 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
418 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
420 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
434 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
441 .name = "BRCM STB PCIe MSI",
590 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
592 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
621 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
625 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
639 msi->base = pcie->base; in brcm_pcie_enable_msi()
640 msi->np = pcie->np; in brcm_pcie_enable_msi()
641 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
643 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
668 pcie->msi = msi; in brcm_pcie_enable_msi()
674 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
676 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
682 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
684 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
694 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
695 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
703 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
708 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
715 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
716 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
724 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
729 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
730 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
733 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
738 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
740 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
743 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
748 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
750 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
753 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
755 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
759 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
761 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
764 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
769 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
771 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
774 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
778 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
780 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
783 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
787 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
789 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
807 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
812 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
813 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
815 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
819 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
820 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
822 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
832 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
837 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
840 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
851 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
870 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
873 void __iomem *base = pcie->base; in brcm_pcie_setup()
881 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
884 if (pcie->type == BCM2711) in brcm_pcie_setup()
885 pcie->perst_set(pcie, 1); in brcm_pcie_setup()
890 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
893 if (is_bmips(pcie)) in brcm_pcie_setup()
906 if (is_bmips(pcie)) in brcm_pcie_setup()
908 else if (pcie->type == BCM2711) in brcm_pcie_setup()
910 else if (pcie->type == BCM7278) in brcm_pcie_setup()
927 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
940 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
941 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
960 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
962 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
964 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
965 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
969 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
974 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
981 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
990 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
997 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
1005 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1009 if (is_bmips(pcie)) { in brcm_pcie_setup()
1013 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1017 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1022 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1028 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1040 * presence of a PCIe access.
1042 static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) in brcm_extend_rbus_timeout() argument
1045 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1049 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1052 static void brcm_config_clkreq(struct brcm_pcie *pcie) in brcm_config_clkreq() argument
1059 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1061 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1066 clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); in brcm_config_clkreq()
1074 * L1SS capable AND the OS enables L1SS, all PCIe traffic in brcm_config_clkreq()
1084 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1086 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1094 * section 3.2.5.2.2 of the PCIe spec. This situation is in brcm_config_clkreq()
1098 brcm_extend_rbus_timeout(pcie); in brcm_config_clkreq()
1106 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1109 writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); in brcm_config_clkreq()
1111 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1114 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1116 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1117 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1123 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1126 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1127 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1136 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1139 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1144 brcm_config_clkreq(pcie); in brcm_pcie_start_link()
1146 if (pcie->gen) in brcm_pcie_start_link()
1147 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1149 if (pcie->ssc) { in brcm_pcie_start_link()
1150 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1192 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1207 pcie->sr = sr; in brcm_pcie_add_bus()
1219 pcie->sr = NULL; in brcm_pcie_add_bus()
1224 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1230 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1231 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1240 pcie->sr = NULL; in brcm_pcie_remove_bus()
1243 /* L23 is a low-power PCIe link state */
1244 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1246 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1266 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1269 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1283 void __iomem *base = pcie->base; in brcm_phy_cntl()
1300 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1305 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1307 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1310 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1312 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1315 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1317 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1320 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1321 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1323 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1335 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1336 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1352 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1353 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1356 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1362 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1365 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1371 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1377 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1379 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1380 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1381 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1382 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1385 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1390 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1397 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1402 base = pcie->base; in brcm_pcie_resume_noirq()
1403 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1407 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1411 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1416 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1426 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1430 if (pcie->sr) { in brcm_pcie_resume_noirq()
1431 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1438 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1440 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1441 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1449 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1453 if (pcie->msi) in brcm_pcie_resume_noirq()
1454 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1459 if (pcie->sr) in brcm_pcie_resume_noirq()
1460 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1462 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1464 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1468 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1470 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1471 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1472 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1473 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1474 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1475 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1476 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1481 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1482 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1486 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1550 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1551 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1552 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1553 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1554 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1555 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1556 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1557 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1582 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1585 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1595 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1596 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1597 pcie->np = np; in brcm_pcie_probe()
1598 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1599 pcie->type = data->type; in brcm_pcie_probe()
1600 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1601 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1603 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1604 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1605 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1607 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1608 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1609 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1612 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1614 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1616 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1621 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1622 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1623 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1624 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1626 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1627 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1628 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1629 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1632 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1636 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1638 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1639 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1643 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1647 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1648 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1649 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1654 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1655 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1656 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1658 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1663 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1664 bridge->sysdata = pcie; in brcm_pcie_probe()
1666 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1669 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1680 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1695 .name = "brcm-pcie",
1703 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");