Lines Matching +full:keystone +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
14 #include <linux/gpio/consumer.h>
31 #include "pcie-designware.h"
54 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
55 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
79 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
105 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
137 return readl(ks_pcie->va_app_base + offset); in ks_pcie_app_readl()
143 writel(val, ks_pcie->va_app_base + offset); in ks_pcie_app_writel()
150 u32 irq = data->hwirq; in ks_pcie_msi_irq_ack()
176 msi_target = ks_pcie->app.start + MSI_IRQ; in ks_pcie_compose_msi_msg()
177 msg->address_lo = lower_32_bits(msi_target); in ks_pcie_compose_msi_msg()
178 msg->address_hi = upper_32_bits(msi_target); in ks_pcie_compose_msi_msg()
179 msg->data = data->hwirq; in ks_pcie_compose_msi_msg()
181 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", in ks_pcie_compose_msi_msg()
182 (int)data->hwirq, msg->address_hi, msg->address_lo); in ks_pcie_compose_msi_msg()
188 return -EINVAL; in ks_pcie_msi_set_affinity()
195 u32 irq = data->hwirq; in ks_pcie_msi_mask()
201 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_mask()
212 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_mask()
219 u32 irq = data->hwirq; in ks_pcie_msi_unmask()
225 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_unmask()
236 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_unmask()
240 .name = "KEYSTONE-PCI-MSI",
250 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; in ks_pcie_msi_host_init()
257 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_handle_intx_irq()
258 struct device *dev = pci->dev; in ks_pcie_handle_intx_irq()
265 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); in ks_pcie_handle_intx_irq()
280 struct device *dev = ks_pcie->pci->dev; in ks_pcie_handle_error_irq()
298 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) in ks_pcie_handle_error_irq()
301 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) in ks_pcie_handle_error_irq()
322 .name = "Keystone-PCI-INTX-IRQ",
333 irq_set_chip_data(irq, d->host_data); in ks_pcie_init_intx_irq_map()
344 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
345 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
365 * ks_pcie_clear_dbi_mode() - Disable DBI mode
366 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
388 u32 num_viewport = ks_pcie->num_viewport; in ks_pcie_setup_rc_app_regs()
389 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_setup_rc_app_regs()
390 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_setup_rc_app_regs()
395 mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; in ks_pcie_setup_rc_app_regs()
396 start = mem->start; in ks_pcie_setup_rc_app_regs()
397 end = mem->end; in ks_pcie_setup_rc_app_regs()
405 if (ks_pcie->is_am6) in ks_pcie_setup_rc_app_regs()
411 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ in ks_pcie_setup_rc_app_regs()
428 struct dw_pcie_rp *pp = bus->sysdata; in ks_pcie_other_map_bus()
433 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | in ks_pcie_other_map_bus()
435 if (!pci_is_root_bus(bus->parent)) in ks_pcie_other_map_bus()
439 return pp->va_cfg0_base + where; in ks_pcie_other_map_bus()
449 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
456 struct dw_pcie_rp *pp = bus->sysdata; in ks_pcie_v3_65_add_bus()
468 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); in ks_pcie_v3_65_add_bus()
476 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); in ks_pcie_v3_65_add_bus()
489 * ks_pcie_link_up() - Check if link up
527 struct pci_bus *bus = dev->bus; in ks_pcie_quirk()
546 bridge = bus->self; in ks_pcie_quirk()
547 bus = bus->parent; in ks_pcie_quirk()
554 * Keystone PCI controller has a h/w limitation of in ks_pcie_quirk()
561 dev_info(&dev->dev, "limiting MRRS to 256\n"); in ks_pcie_quirk()
570 unsigned int irq = desc->irq_data.hwirq; in ks_pcie_msi_irq_handler()
572 u32 offset = irq - ks_pcie->msi_host_irq; in ks_pcie_msi_irq_handler()
573 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_msi_irq_handler()
574 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_msi_irq_handler()
575 struct device *dev = pci->dev; in ks_pcie_msi_irq_handler()
590 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit in ks_pcie_msi_irq_handler()
599 generic_handle_domain_irq(pp->irq_domain, vector); in ks_pcie_msi_irq_handler()
606 * ks_pcie_intx_irq_handler() - Handle INTX interrupt
616 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_intx_irq_handler()
617 struct device *dev = pci->dev; in ks_pcie_intx_irq_handler()
618 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; in ks_pcie_intx_irq_handler()
635 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_msi_irq()
636 struct device_node *np = ks_pcie->np; in ks_pcie_config_msi_irq()
644 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); in ks_pcie_config_msi_irq()
646 if (ks_pcie->is_am6) in ks_pcie_config_msi_irq()
648 dev_warn(dev, "msi-interrupt-controller node is absent\n"); in ks_pcie_config_msi_irq()
649 return -EINVAL; in ks_pcie_config_msi_irq()
654 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); in ks_pcie_config_msi_irq()
655 ret = -EINVAL; in ks_pcie_config_msi_irq()
662 ret = -EINVAL; in ks_pcie_config_msi_irq()
666 if (!ks_pcie->msi_host_irq) { in ks_pcie_config_msi_irq()
669 ret = -EINVAL; in ks_pcie_config_msi_irq()
672 ks_pcie->msi_host_irq = irq_data->hwirq; in ks_pcie_config_msi_irq()
689 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_intx_irq()
691 struct device_node *np = ks_pcie->np; in ks_pcie_config_intx_irq()
695 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); in ks_pcie_config_intx_irq()
698 * Since INTX interrupts are modeled as edge-interrupts in in ks_pcie_config_intx_irq()
701 if (ks_pcie->is_am6) in ks_pcie_config_intx_irq()
703 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); in ks_pcie_config_intx_irq()
704 return -EINVAL; in ks_pcie_config_intx_irq()
709 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); in ks_pcie_config_intx_irq()
710 ret = -EINVAL; in ks_pcie_config_intx_irq()
717 ret = -EINVAL; in ks_pcie_config_intx_irq()
720 ks_pcie->intx_host_irqs[i] = irq; in ks_pcie_config_intx_irq()
731 ret = -EINVAL; in ks_pcie_config_intx_irq()
734 ks_pcie->intx_irq_domain = intx_irq_domain; in ks_pcie_config_intx_irq()
746 * When a PCI device does not exist during config cycles, keystone host
758 regs->uregs[reg] = -1; in ks_pcie_fault()
759 regs->ARM_pc += 4; in ks_pcie_fault()
771 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_init_id()
772 struct device *dev = pci->dev; in ks_pcie_init_id()
773 struct device_node *np = dev->of_node; in ks_pcie_init_id()
777 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); in ks_pcie_init_id()
782 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); in ks_pcie_init_id()
804 pp->bridge->ops = &ks_pcie_ops; in ks_pcie_host_init()
805 if (!ks_pcie->is_am6) in ks_pcie_host_init()
806 pp->bridge->child_ops = &ks_child_pcie_ops; in ks_pcie_host_init()
819 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
875 ep->page_size = AM654_WIN_SIZE; in ks_pcie_am654_ep_init()
877 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); in ks_pcie_am654_ep_init()
883 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_am654_raise_intx_irq()
916 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in ks_pcie_am654_raise_irq()
917 return -EINVAL; in ks_pcie_am654_raise_irq()
950 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy()
952 while (num_lanes--) { in ks_pcie_disable_phy()
953 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
954 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
962 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy()
965 ret = phy_reset(ks_pcie->phy[i]); in ks_pcie_enable_phy()
969 ret = phy_init(ks_pcie->phy[i]); in ks_pcie_enable_phy()
973 ret = phy_power_on(ks_pcie->phy[i]); in ks_pcie_enable_phy()
975 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
983 while (--i >= 0) { in ks_pcie_enable_phy()
984 phy_power_off(ks_pcie->phy[i]); in ks_pcie_enable_phy()
985 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
993 struct device_node *np = dev->of_node; in ks_pcie_set_mode()
1001 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_set_mode()
1006 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_set_mode()
1025 struct device_node *np = dev->of_node; in ks_pcie_am654_set_mode()
1033 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_am654_set_mode()
1038 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_am654_set_mode()
1053 return -EINVAL; in ks_pcie_am654_set_mode()
1086 .compatible = "ti,keystone-pcie",
1090 .compatible = "ti,am654-pcie-rc",
1094 .compatible = "ti,am654-pcie-ep",
1103 struct device *dev = &pdev->dev; in ks_pcie_probe()
1104 struct device_node *np = dev->of_node; in ks_pcie_probe()
1124 return -EINVAL; in ks_pcie_probe()
1126 version = data->version; in ks_pcie_probe()
1127 host_ops = data->host_ops; in ks_pcie_probe()
1128 ep_ops = data->ep_ops; in ks_pcie_probe()
1129 mode = data->mode; in ks_pcie_probe()
1133 return -ENOMEM; in ks_pcie_probe()
1137 return -ENOMEM; in ks_pcie_probe()
1140 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); in ks_pcie_probe()
1141 if (IS_ERR(ks_pcie->va_app_base)) in ks_pcie_probe()
1142 return PTR_ERR(ks_pcie->va_app_base); in ks_pcie_probe()
1144 ks_pcie->app = *res; in ks_pcie_probe()
1151 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) in ks_pcie_probe()
1152 ks_pcie->is_am6 = true; in ks_pcie_probe()
1154 pci->dbi_base = base; in ks_pcie_probe()
1155 pci->dbi_base2 = base; in ks_pcie_probe()
1156 pci->dev = dev; in ks_pcie_probe()
1157 pci->ops = &ks_pcie_dw_pcie_ops; in ks_pcie_probe()
1158 pci->version = version; in ks_pcie_probe()
1165 "ks-pcie-error-irq", ks_pcie); in ks_pcie_probe()
1172 ret = of_property_read_u32(np, "num-lanes", &num_lanes); in ks_pcie_probe()
1178 return -ENOMEM; in ks_pcie_probe()
1182 return -ENOMEM; in ks_pcie_probe()
1185 snprintf(name, sizeof(name), "pcie-phy%d", i); in ks_pcie_probe()
1195 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); in ks_pcie_probe()
1197 ret = -EINVAL; in ks_pcie_probe()
1202 ks_pcie->np = np; in ks_pcie_probe()
1203 ks_pcie->pci = pci; in ks_pcie_probe()
1204 ks_pcie->link = link; in ks_pcie_probe()
1205 ks_pcie->num_lanes = num_lanes; in ks_pcie_probe()
1206 ks_pcie->phy = phy; in ks_pcie_probe()
1212 if (ret != -EPROBE_DEFER) in ks_pcie_probe()
1213 dev_err(dev, "Failed to get reset GPIO\n"); in ks_pcie_probe()
1219 phy_pm_runtime_get_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1225 phy_pm_runtime_put_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1250 ret = -ENODEV; in ks_pcie_probe()
1254 ret = of_property_read_u32(np, "num-viewport", &num_viewport); in ks_pcie_probe()
1256 dev_err(dev, "unable to read *num-viewport* property\n"); in ks_pcie_probe()
1273 ks_pcie->num_viewport = num_viewport; in ks_pcie_probe()
1274 pci->pp.ops = host_ops; in ks_pcie_probe()
1275 ret = dw_pcie_host_init(&pci->pp); in ks_pcie_probe()
1281 ret = -ENODEV; in ks_pcie_probe()
1285 pci->ep.ops = ep_ops; in ks_pcie_probe()
1286 ret = dw_pcie_ep_init(&pci->ep); in ks_pcie_probe()
1304 while (--i >= 0 && link[i]) in ks_pcie_probe()
1313 struct device_link **link = ks_pcie->link; in ks_pcie_remove()
1314 int num_lanes = ks_pcie->num_lanes; in ks_pcie_remove()
1315 struct device *dev = &pdev->dev; in ks_pcie_remove()
1320 while (num_lanes--) in ks_pcie_remove()
1328 .name = "keystone-pcie",