Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
23 #include "pcie-cadence.h"
28 #define LINK_DOWN BIT(1)
35 #define LINK_STATUS GENMASK(1, 0)
47 #define GENERATION_SEL_MASK GENMASK(1, 0)
67 unsigned int quirk_retrain_flag:1;
68 unsigned int quirk_detect_quiet_flag:1;
69 unsigned int quirk_disable_flr:1;
71 unsigned int byte_access_allowed:1;
75 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
77 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
80 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
83 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
86 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
88 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
91 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_intd_writel() argument
94 writel(value, pcie->intd_cfg_base + offset); in j721e_pcie_intd_writel()
99 struct j721e_pcie *pcie = priv; in j721e_pcie_link_irq_handler() local
100 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_link_irq_handler()
103 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); in j721e_pcie_link_irq_handler()
104 if (!(reg & pcie->linkdown_irq_regfield)) in j721e_pcie_link_irq_handler()
109 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); in j721e_pcie_link_irq_handler()
113 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) in j721e_pcie_config_link_irq() argument
117 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); in j721e_pcie_config_link_irq()
118 reg |= pcie->linkdown_irq_regfield; in j721e_pcie_config_link_irq()
119 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); in j721e_pcie_config_link_irq()
124 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); in j721e_pcie_start_link() local
127 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); in j721e_pcie_start_link()
129 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); in j721e_pcie_start_link()
136 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); in j721e_pcie_stop_link() local
139 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); in j721e_pcie_stop_link()
141 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); in j721e_pcie_stop_link()
146 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); in j721e_pcie_link_up() local
149 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); in j721e_pcie_link_up()
163 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, in j721e_pcie_set_mode() argument
166 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_set_mode()
168 u32 mode = pcie->mode; in j721e_pcie_set_mode()
177 dev_err(dev, "failed to set pcie mode\n"); in j721e_pcie_set_mode()
182 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, in j721e_pcie_set_link_speed() argument
185 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_set_link_speed()
186 struct device_node *np = dev->of_node; in j721e_pcie_set_link_speed()
195 val = link_speed - 1; in j721e_pcie_set_link_speed()
203 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, in j721e_pcie_set_lane_count() argument
206 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_set_lane_count()
207 u32 lanes = pcie->num_lanes; in j721e_pcie_set_lane_count()
212 if (pcie->max_lanes == 4) in j721e_pcie_set_lane_count()
215 val = LANE_COUNT(lanes - 1); in j721e_pcie_set_lane_count()
223 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) in j721e_pcie_ctrl_init() argument
225 struct device *dev = pcie->cdns_pcie->dev; in j721e_pcie_ctrl_init()
226 struct device_node *node = dev->of_node; in j721e_pcie_ctrl_init()
232 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); in j721e_pcie_ctrl_init()
234 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); in j721e_pcie_ctrl_init()
239 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, in j721e_pcie_ctrl_init()
244 ret = j721e_pcie_set_mode(pcie, syscon, offset); in j721e_pcie_ctrl_init()
250 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); in j721e_pcie_ctrl_init()
256 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); in j721e_pcie_ctrl_init()
258 dev_err(dev, "Failed to set num-lanes\n"); in j721e_pcie_ctrl_init()
324 .max_lanes = 1,
330 .max_lanes = 1,
349 .compatible = "ti,j721e-pcie-host",
353 .compatible = "ti,j721e-pcie-ep",
357 .compatible = "ti,j7200-pcie-host",
361 .compatible = "ti,j7200-pcie-ep",
365 .compatible = "ti,am64-pcie-host",
369 .compatible = "ti,am64-pcie-ep",
373 .compatible = "ti,j784s4-pcie-host",
377 .compatible = "ti,j784s4-pcie-ep",
385 struct device *dev = &pdev->dev; in j721e_pcie_probe()
386 struct device_node *node = dev->of_node; in j721e_pcie_probe()
390 struct j721e_pcie *pcie; in j721e_pcie_probe() local
403 return -EINVAL; in j721e_pcie_probe()
405 mode = (u32)data->mode; in j721e_pcie_probe()
407 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in j721e_pcie_probe()
408 if (!pcie) in j721e_pcie_probe()
409 return -ENOMEM; in j721e_pcie_probe()
414 return -ENODEV; in j721e_pcie_probe()
418 return -ENOMEM; in j721e_pcie_probe()
420 if (!data->byte_access_allowed) in j721e_pcie_probe()
421 bridge->ops = &cdns_ti_pcie_host_ops; in j721e_pcie_probe()
423 rc->quirk_retrain_flag = data->quirk_retrain_flag; in j721e_pcie_probe()
424 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; in j721e_pcie_probe()
426 cdns_pcie = &rc->pcie; in j721e_pcie_probe()
427 cdns_pcie->dev = dev; in j721e_pcie_probe()
428 cdns_pcie->ops = &j721e_pcie_ops; in j721e_pcie_probe()
429 pcie->cdns_pcie = cdns_pcie; in j721e_pcie_probe()
433 return -ENODEV; in j721e_pcie_probe()
437 return -ENOMEM; in j721e_pcie_probe()
439 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; in j721e_pcie_probe()
440 ep->quirk_disable_flr = data->quirk_disable_flr; in j721e_pcie_probe()
442 cdns_pcie = &ep->pcie; in j721e_pcie_probe()
443 cdns_pcie->dev = dev; in j721e_pcie_probe()
444 cdns_pcie->ops = &j721e_pcie_ops; in j721e_pcie_probe()
445 pcie->cdns_pcie = cdns_pcie; in j721e_pcie_probe()
452 pcie->mode = mode; in j721e_pcie_probe()
453 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; in j721e_pcie_probe()
458 pcie->intd_cfg_base = base; in j721e_pcie_probe()
463 pcie->user_cfg_base = base; in j721e_pcie_probe()
465 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in j721e_pcie_probe()
466 if (ret || num_lanes > data->max_lanes) { in j721e_pcie_probe()
467 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); in j721e_pcie_probe()
468 num_lanes = 1; in j721e_pcie_probe()
471 pcie->num_lanes = num_lanes; in j721e_pcie_probe()
472 pcie->max_lanes = data->max_lanes; in j721e_pcie_probe()
475 return -EINVAL; in j721e_pcie_probe()
481 dev_set_drvdata(dev, pcie); in j721e_pcie_probe()
489 ret = j721e_pcie_ctrl_init(pcie); in j721e_pcie_probe()
496 "j721e-pcie-link-down-irq", pcie); in j721e_pcie_probe()
502 j721e_pcie_config_link_irq(pcie); in j721e_pcie_probe()
509 if (ret != -EPROBE_DEFER) in j721e_pcie_probe()
532 pcie->refclk = clk; in j721e_pcie_probe()
544 gpiod_set_value_cansleep(gpiod, 1); in j721e_pcie_probe()
549 clk_disable_unprepare(pcie->refclk); in j721e_pcie_probe()
582 struct j721e_pcie *pcie = platform_get_drvdata(pdev); in j721e_pcie_remove() local
583 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; in j721e_pcie_remove()
584 struct device *dev = &pdev->dev; in j721e_pcie_remove()
586 clk_disable_unprepare(pcie->refclk); in j721e_pcie_remove()
596 .name = "j721e-pcie",