realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
27 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
40 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
48 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
56 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
68 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
77 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
94 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
98 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
105 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
108 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
111 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
114 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
115 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
116 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
117 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
121 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
122 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
128 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
129 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
135 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
136 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
143 #define BE_TXD_BODY0_HWAMSDU BIT(5)
144 #define BE_TXD_BODY0_HW_SEC_IV BIT(6)
145 #define BE_TXD_BODY0_WD_PAGE BIT(7)
146 #define BE_TXD_BODY0_CHK_EN BIT(8)
147 #define BE_TXD_BODY0_WP_INT BIT(9)
148 #define BE_TXD_BODY0_STF_MODE BIT(10)
150 #define BE_TXD_BODY0_CH_DMA GENMASK(19, 16)
151 #define BE_TXD_BODY0_SMH_EN BIT(20)
152 #define BE_TXD_BODY0_PKT_OFFSET BIT(21)
153 #define BE_TXD_BODY0_WDINFO_EN BIT(22)
154 #define BE_TXD_BODY0_MOREDATA BIT(23)
156 #define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28)
158 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
164 #define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16)
165 #define BE_TXD_BODY1_SW_SEC_IV BIT(18)
172 #define BE_TXD_BODY2_AGG_EN BIT(14)
173 #define BE_TXD_BODY2_BK BIT(15)
174 #define BE_TXD_BODY2_MACID_EXTEND BIT(16)
176 #define BE_TXD_BODY2_TID_IND BIT(23)
181 #define BE_TXD_BODY3_MLO_FLAG BIT(12)
182 #define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
183 #define BE_TXD_BODY3_TRY_RATE BIT(14)
184 #define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
185 #define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16)
187 #define BE_TXD_BODY3_RU_RTY BIT(28)
188 #define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
189 #define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
190 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
194 #define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16)
200 #define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16)
206 #define BE_TXD_BODY6_PS160 BIT(10)
207 #define BE_TXD_BODY6_BMC BIT(11)
208 #define BE_TXD_BODY6_NO_ACK BIT(12)
209 #define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13)
210 #define BE_TXD_BODY6_A4_HDR BIT(14)
211 #define BE_TXD_BODY6_EOSP_BIT BIT(15)
212 #define BE_TXD_BODY6_S_IDX GENMASK(23, 16)
218 #define BE_TXD_BODY7_DATA_ER BIT(10)
219 #define BE_TXD_BODY7_DATA_BW_ER BIT(11)
220 #define BE_TXD_BODY7_DATA_DCM BIT(12)
222 #define BE_TXD_BODY7_DATARATE GENMASK(27, 16)
224 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
229 #define BE_TXD_INFO0_DISRTSFB BIT(9)
230 #define BE_TXD_INFO0_DISDATAFB BIT(10)
231 #define BE_TXD_INFO0_DATA_LDPC BIT(11)
232 #define BE_TXD_INFO0_DATA_STBC BIT(12)
233 #define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16)
234 #define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22)
235 #define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23)
236 #define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30)
237 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
242 #define BE_TXD_INFO1_NAVUSEHDR BIT(10)
243 #define BE_TXD_INFO1_A_CTRL_BQR BIT(12)
244 #define BE_TXD_INFO1_A_CTRL_BSR BIT(14)
245 #define BE_TXD_INFO1_A_CTRL_CAS BIT(15)
246 #define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16)
251 #define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
253 #define BE_TXD_INFO2_FORCE_TXOP BIT(17)
255 #define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21)
257 #define BE_TXD_INFO2_SPE_RPT_V1 BIT(30)
258 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
263 #define BE_TXD_INFO3_CQI_SND BIT(8)
264 #define BE_TXD_INFO3_RTT_EN BIT(9)
265 #define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
266 #define BE_TXD_INFO3_BT_NULL BIT(11)
267 #define BE_TXD_INFO3_TRI_FRAME BIT(12)
268 #define BE_TXD_INFO3_NULL_0 BIT(13)
269 #define BE_TXD_INFO3_NULL_1 BIT(14)
270 #define BE_TXD_INFO3_RAW BIT(15)
271 #define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16)
272 #define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25)
273 #define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26)
275 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
279 #define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16)
280 #define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
281 #define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
283 #define BE_TXD_INFO4_RTS_EN BIT(27)
284 #define BE_TXD_INFO4_CTS2SELF BIT(28)
286 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
290 #define BE_TXD_INFO5_SR_EN_V1 BIT(5)
291 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
296 #define BE_TXD_INFO6_UL_DOPPLER BIT(15)
297 #define BE_TXD_INFO6_UL_STBC BIT(16)
302 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
304 #define BE_TXD_INFO7_ELNA_IDX BIT(8)
308 #define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16)
318 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
319 #define AX_RXD_BB_SEL BIT(22)
320 #define AX_RXD_MAC_INFO_VLD BIT(23)
323 #define AX_RXD_LONG_RXD BIT(31)
328 #define AX_RXD_SR_EN BIT(7)
331 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
333 #define AX_RXD_NON_SRG_PPDU BIT(28)
334 #define AX_RXD_INTER_PPDU BIT(29)
335 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
336 #define AX_RXD_INTER_PPDU_v1 BIT(15)
344 #define AX_RXD_A1_MATCH BIT(0)
345 #define AX_RXD_SW_DEC BIT(1)
346 #define AX_RXD_HW_DEC BIT(2)
347 #define AX_RXD_AMPDU BIT(3)
348 #define AX_RXD_AMPDU_END_PKT BIT(4)
349 #define AX_RXD_AMSDU BIT(5)
350 #define AX_RXD_AMSDU_CUT BIT(6)
351 #define AX_RXD_LAST_MSDU BIT(7)
352 #define AX_RXD_BYPASS BIT(8)
353 #define AX_RXD_CRC32_ERR BIT(9)
354 #define AX_RXD_ICV_ERR BIT(10)
355 #define AX_RXD_MAGIC_WAKE BIT(11)
356 #define AX_RXD_UNICAST_WAKE BIT(12)
357 #define AX_RXD_PATTERN_WAKE BIT(13)
359 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
361 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
362 #define AX_RXD_WITH_LLC BIT(25)
363 #define AX_RXD_RX_STATISTICS BIT(26)
367 #define AX_RXD_MC BIT(2)
368 #define AX_RXD_BC BIT(3)
369 #define AX_RXD_MD BIT(4)
370 #define AX_RXD_MF BIT(5)
371 #define AX_RXD_PWR BIT(6)
372 #define AX_RXD_QOS BIT(7)
374 #define AX_RXD_EOSP BIT(12)
375 #define AX_RXD_HTC BIT(13)
376 #define AX_RXD_QNULL BIT(14)
377 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
383 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
385 #define AX_RXD_ADDR_CAM_VLD BIT(28)
386 #define AX_RXD_ADDR_FWD_EN BIT(29)
387 #define AX_RXD_RX_PL_MATCH BIT(30)
394 #define AX_RXD_SMART_ANT BIT(16)
396 #define AX_RXD_HDR_CNV BIT(21)
398 #define AX_RXD_BIP_KEYID BIT(27)
399 #define AX_RXD_BIP_ENC BIT(28)
405 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
406 #define RTW89_RXINFO_USER_DATA BIT(1)
407 #define RTW89_RXINFO_USER_CTRL BIT(2)
408 #define RTW89_RXINFO_USER_MGMT BIT(3)
409 #define RTW89_RXINFO_USER_BCM BIT(4)
421 #define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16)
422 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
423 #define RTW89_RXINFO_W0_INVALID_V1 BIT(27)
424 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
425 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
428 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
436 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
441 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
458 #define BE_RXD_BB_SEL BIT(30)
459 #define BE_RXD_LONG_RXD BIT(31)
463 #define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16)
465 #define BE_RXD_FW_RLS BIT(26)
470 #define BE_RXD_LAST_MSDU BIT(12)
471 #define BE_RXD_AMSDU_CUT BIT(13)
472 #define BE_RXD_ADDR_CAM_VLD BIT(14)
473 #define BE_RXD_REORDER BIT(15)
474 #define BE_RXD_SEQ_MASK GENMASK(27, 16)
479 #define BE_RXD_BIP_KEYID BIT(4)
480 #define BE_RXD_BIP_ENC BIT(5)
481 #define BE_RXD_CRC32_ERR BIT(6)
482 #define BE_RXD_ICV_ERR BIT(7)
483 #define BE_RXD_HW_DEC BIT(8)
484 #define BE_RXD_SW_DEC BIT(9)
485 #define BE_RXD_A1_MATCH BIT(10)
486 #define BE_RXD_AMPDU BIT(11)
487 #define BE_RXD_AMPDU_EOF BIT(12)
488 #define BE_RXD_AMSDU BIT(13)
489 #define BE_RXD_MC BIT(14)
490 #define BE_RXD_BC BIT(15)
491 #define BE_RXD_MD BIT(16)
492 #define BE_RXD_MF BIT(17)
493 #define BE_RXD_PWR BIT(18)
494 #define BE_RXD_QOS BIT(19)
495 #define BE_RXD_EOSP BIT(20)
496 #define BE_RXD_HTC BIT(21)
497 #define BE_RXD_QNULL BIT(22)
498 #define BE_RXD_A4_FRAME BIT(23)
506 #define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16)
507 #define BE_RXD_RX_REORDER_FIELD_EN BIT(19)
515 #define BE_RXD_SR_EN BIT(13)
516 #define BE_RXD_NON_SRG_PPDU BIT(14)
517 #define BE_RXD_INTER_PPDU BIT(15)
518 #define BE_RXD_USER_ID_MASK GENMASK(21, 16)
519 #define BE_RXD_RX_STATISTICS BIT(22)
520 #define BE_RXD_SMART_ANT BIT(23)
525 #define BE_RXD_MAGIC_WAKE BIT(5)
526 #define BE_RXD_UNICAST_WAKE BIT(6)
527 #define BE_RXD_PATTERN_WAKE BIT(7)
528 #define BE_RXD_RX_PL_MATCH BIT(8)
530 #define BE_RXD_HDR_CNV BIT(16)
531 #define BE_RXD_NAT25_HIT BIT(17)
532 #define BE_RXD_IS_DA BIT(18)
533 #define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19)
535 #define BE_RXD_RXSC_HIT BIT(23)
536 #define BE_RXD_WITH_LLC BIT(24)
537 #define BE_RXD_RX_AGG_FIELD_EN BIT(25)
544 #define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16)
553 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
558 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
577 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
586 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1