Lines Matching +full:7 +full:- +full:31

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
22 #define B_AX_SOP_ASWRM BIT(31)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
70 #define B_AX_EF_ENT BIT(31)
92 #define B_AX_BTMODE_MASK GENMASK(7, 6)
103 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
146 #define B_AX_TOGGLE BIT(31)
154 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
165 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
169 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
190 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
212 #define B_AX_EN_32K BIT(31)
216 #define B_AX_UDM1_MASK GENMASK(31, 16)
219 #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
239 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
248 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
254 #define B_AX_XTAL_SC_LPS BIT(31)
268 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
271 #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
291 #define B_AX_WLRF_CTRL_7 BIT(7)
297 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
317 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
329 #define B_AX_TXHCI_EN_V1 BIT(7)
389 #define B_AX_LTR_REQ_DRV BIT(7)
488 #define B_AX_DMAC_CRPRT BIT(31)
528 #define PCI_LTR_IDLE_TIMER_3_2MS 7
560 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
577 #define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7)
601 #define B_AX_PKTIN_ERR_INT_EN BIT(7)
609 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
620 #define B_AX_PKTIN_ERR_FLAG BIT(7)
639 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
661 #define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7)
704 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
726 #define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
771 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
792 #define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
853 #define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
933 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
952 #define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
997 #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
1006 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
1018 #define B_AX_GRP BIT(31)
1082 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1085 #define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
1105 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1166 #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1235 #define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7)
1257 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1264 #define B_AX_WDE_DFI_ACTIVE BIT(31)
1268 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1276 #define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7)
1286 #define B_AX_PLE_LOCKON_DLEPIF07 BIT(7)
1296 #define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
1304 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1309 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1320 #define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7)
1341 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1391 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1472 #define B_AX_PLE_DFI_ACTIVE BIT(31)
1476 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1490 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1543 #define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7)
1553 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1579 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1612 #define B_AX_WD_BUF_REQ_EXEC BIT(31)
1618 #define B_AX_WD_BUF_STAT_DONE BIT(31)
1624 #define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1627 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1643 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1676 #define B_AX_TX_LLC_PRE_ERR_EN BIT(7)
1746 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1768 #define B_AX_SS_INIT_DONE_1 BIT(31)
1774 #define B_AX_SS_UL_REL BIT(31)
1783 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1787 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1791 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1795 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1846 #define B_AX_DFI_ACTIVE BIT(31)
1850 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1853 #define B_AX_B0_PRELD_FEN BIT(31)
1863 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1914 #define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7)
1924 #define B_AX_B1_PRELD_FEN BIT(31)
1932 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1983 #define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7)
2010 #define B_AX_CMAC_CRPRT BIT(31)
2024 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2057 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2064 #define B_AX_RSC_MASK GENMASK(7, 6)
2069 #define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
2076 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2077 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2083 #define B_AX_WMAC_TX_ERR_IND BIT(7)
2111 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2116 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2121 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2126 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2162 #define B_AX_CTN_TXEN_VO_1 BIT(7)
2174 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2176 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2193 #define B_AX_TB_CHK_TX_NAV BIT(31)
2208 #define B_AX_CTN_CHK_INTRA_NAV BIT(7)
2234 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2238 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2257 #define B_AX_BCNERR_CNT_EN BIT(7)
2272 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2318 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2325 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2328 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2349 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2365 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2372 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2379 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2401 #define B_AX_P0MB7_EN BIT(7)
2418 #define B_AX_MGQ_LIFETIME_EN BIT(7)
2427 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2430 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2434 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2436 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2441 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2446 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2451 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2459 #define B_AX_ADD_TXCNT_BY BIT(31)
2475 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2484 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2487 #define B_AX_RX_PLT_GNT_LTE_RX BIT(7)
2509 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2527 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2564 #define B_AX_PTCL_TX_ON_STAT BIT(7)
2574 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2578 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2596 #define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
2620 #define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7)
2631 #define B_AX_RXDMA_DBGOUT_EN BIT(31)
2639 #define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7)
2653 #define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
2664 #define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
2670 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
2684 #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2723 #define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7)
2784 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2825 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2832 #define B_AX_TCR_PADSEL BIT(7)
2843 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2852 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2856 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2872 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2877 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2891 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2895 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2908 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2912 #define B_AX_WMAC_RESP_STBC_EN BIT(31)
2926 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
2934 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
2959 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
2963 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2975 #define B_AX_RMAC_CSI BIT(7)
3004 #define B_AX_CSI_ERROR_FLAG_CLR BIT(7)
3019 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3023 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3038 #define B_AX_TMAC_MACTX_INT_EN BIT(7)
3052 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3103 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3111 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3143 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
3169 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3184 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3195 #define B_AX_A_BCN_CHK_EN BIT(7)
3256 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3257 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3259 #define B_AX_STATE_UPD BIT(7)
3264 #define B_AX_RXERR_INTPS_EN BIT(31)
3273 #define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7)
3298 #define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7)
3329 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3330 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3335 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3379 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3382 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3383 #define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)
3386 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3387 #define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)
3415 #define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28)
3421 #define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4)
3454 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3463 #define B_AX_BTC_EN BIT(31)
3471 #define B_AX_IGN_GNT_BT2_RX BIT(7)
3487 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3520 #define B_AX_TIMER_MASK GENMASK(7, 0)
3530 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3540 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3544 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3562 #define B_AX_GNT_WL_RFC_S1_VAL BIT(7)
3585 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3587 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3597 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3614 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3634 #define B_AX_LTECOEX_FUN_EN BIT(7)
3643 #define B_AX_GNT_WL_RX_SW_VAL BIT(7)
3661 #define B_BE_ISO_DIOE BIT(7)
3670 #define B_BE_SOP_ASWRM BIT(31)
3693 #define B_BE_CHIP_PDN_EN BIT(7)
3701 #define B_BE_WL_CLK_TEST BIT(7)
3736 #define B_BE_DIS_CLK_REG7_GATE BIT(7)
3756 #define B_BE_FORCE_MACBBBT_PWR_ON BIT(31)
3774 #define B_BE_R_SYM_WLBBOFF1_P2_PC_EN BIT(7)
3817 #define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
3823 #define B_BE_EF_DATA_MASK GENMASK(31, 0)
3826 #define B_BE_ISO_BD2PP BIT(31)
3865 #define B_BE_USBA_FORCE_PWR_NGAT BIT(7)
3875 #define B_BE_HCI_WLAN_IO_ST BIT(31)
3896 #define B_BE_SDIO_PAD_E_MASK GENMASK(7, 5)
3928 #define B_BE_R_SYM_FEN_WLMACOFF BIT(31)
3954 #define B_BE_UART_EN BIT(7)
3978 #define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4)
3985 #define B_BE_LPSROP_DMEM5_RSU_EN BIT(31)
4004 #define B_BE_LPSROP_LOWPWRPLL BIT(7)
4008 #define B_BE_EF_ENT BIT(31)
4024 #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
4028 #define B_BE_SYM_REG_PCIE_WRMSK BIT(7)
4043 #define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
4046 #define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4055 #define B_BE_HALT_H2C_MASK GENMASK(31, 0)
4058 #define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28)
4085 #define B_BE_FS_GPIO23_INT_EN BIT(7)
4112 #define B_BE_GPIO7_INT_EN BIT(7)
4139 #define B_BE_GPIO7_INT BIT(7)
4149 #define B_BE_RUN_ENV_MASK GENMASK(31, 30)
4159 #define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4)
4168 #define B_BE_EN_32K BIT(31)
4172 #define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28)
4175 #define B_BE_NULL_POINTER_INDC BIT(7)
4184 #define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16)
4187 #define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
4191 #define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4194 #define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
4208 #define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29)
4220 #define B_BE_REG_LPF_C2_FAST_MASK GENMASK(7, 5)
4225 #define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30)
4239 #define B_BE_REG_12LDO_SEL_MASK GENMASK(7, 6)
4247 #define B_BE_WL_XTAL_SI_CMD_POLL BIT(31)
4252 #define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
4258 #define B_BE_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
4268 #define B_BE_DCPU_UART_EN BIT(7)
4305 #define B_BE_WLAN_WDT_TIMEOUT BIT(31)
4311 #define B_BE_AXIDMA_WDT_TIMEOUT BIT(31)
4317 #define B_BE_AON_WDT_TIMEOUT BIT(31)
4335 #define B_BE_LOCAL_WDT_TIMEOUT BIT(31)
4341 #define B_BE_MDIO_WDT_TIMEOUT BIT(31)
4347 #define B_BE_LA_MODE_WDT_TIMEOUT BIT(31)
4353 #define B_BE_WDT_AR_TIMEOUT BIT(31)
4359 #define B_BE_WDT_AW_TIMEOUT BIT(31)
4365 #define B_BE_WDT_W_TIMEOUT BIT(31)
4371 #define B_BE_WDT_B_TIMEOUT BIT(31)
4377 #define B_BE_WDT_R_TIMEOUT BIT(31)
4383 #define B_BE_ENABLE_LTR_CTL_DECISION BIT(31)
4405 #define B_BE_HCI_CR_PROTECT BIT(31)
4411 #define B_BE_DMAC_CRPRT BIT(31)
4433 #define B_BE_LTR_CTL_EN BIT(7)
4479 #define B_BE_HWAMSDU_PADDING_MODE BIT(31)
4486 #define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)
4512 #define B_BE_WDE_EMPTY_QUE_OTHERS BIT(7)
4536 #define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)
4539 #define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0)
4542 #define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)
4545 #define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0)
4548 #define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)
4551 #define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0)
4554 #define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)
4557 #define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0)
4560 #define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)
4564 #define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)
4567 #define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)
4570 #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)
4586 #define B_BE_PKTIN_ERR_INT_EN BIT(7)
4607 #define B_BE_PKTIN_ERR_FLAG BIT(7)
4617 #define B_BE_REUSE_SIZE_ERR BIT(31)
4640 #define B_BE_HDR_DMA_TIMEOUT_ERR BIT(7)
4649 #define B_BE_HR_WRFF_UNDERFLOW_ERR BIT(31)
4670 #define B_BE_HT_OFFSET_UNMATCH_ERR BIT(7)
4700 #define B_BE_F2P_TOTAL_NUM_ERR BIT(7)
4709 #define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31)
4732 #define B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
4777 #define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
4798 #define B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
4875 #define B_BE_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
4928 #define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)
4940 #define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6)
4971 #define B_BE_WDE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5087 #define B_BE_PLE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5216 #define B_BE_PLE_DFI_ACTIVE BIT(31)
5221 #define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
5224 #define B_BE_WDRLS_DIS_AGAC BIT(31)
5226 #define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6)
5268 #define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
5321 #define B_BE_WD_BUF_REQ_EXEC BIT(31)
5326 #define B_BE_WD_BUF_STAT_DONE BIT(31)
5330 #define B_BE_WD_CPUQ_OP_EXEC BIT(31)
5332 #define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5349 #define B_BE_WD_CPUQ_OP_STAT_DONE BIT(31)
5354 #define B_BE_PL_BUF_REQ_EXEC BIT(31)
5359 #define B_BE_PL_BUF_STAT_DONE BIT(31)
5363 #define B_BE_PL_CPUQ_OP_EXEC BIT(31)
5365 #define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5382 #define B_BE_PL_CPUQ_OP_STAT_DONE BIT(31)
5433 #define B_BE_EN_CUT_AMSDU BIT(31)
5456 #define B_BE_SEC_ENG_EN BIT(31)
5482 #define B_BE_STOP_RX_PKT_HANDLE BIT(7)
5492 #define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16)
5499 #define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)
5502 #define B_BE_DBG_READ_MASK GENMASK(31, 0)
5530 #define B_BE_MPDUINFO_FEN BIT(31)
5536 #define B_BE_B0_PRELD_FEN BIT(31)
5543 #define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5576 #define B_BE_B1_PRELD_FEN BIT(31)
5583 #define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5616 #define B_BE_MLO_TABLE_INIT_DONE BIT(31)
5622 #define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31)
5634 #define B_BE_MLO_ISR_IDCT_0 BIT(31)
5651 #define B_BE_SS_INIT_DONE BIT(31)
5666 #define B_BE_MRT_SRAM_EN BIT(7)
5691 #define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
5705 #define B_BE_STOP_AXI_MST BIT(7)
5713 #define B_BE_STOP_WPDMA BIT(31)
5721 #define B_BE_STOP_CH7 BIT(7)
5731 #define B_BE_HAXI_RRESP_ERR_IDCT_MSK BIT(7)
5755 #define B_BE_HAXI_RRESP_ERR_IDCT BIT(7)
5770 #define B_BE_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
5809 #define B_BE_CMAC_SHARE_CRPRT BIT(31)
5819 #define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)
5820 #define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4)
5827 #define B_BE_CMAC_CRPRT BIT(31)
5843 #define B_BE_RESP_PKTCTL_EN BIT(7)
5863 #define B_BE_RESP_PKTCTL_CKEN BIT(7)
5878 #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)
5887 #define B_BE_TXSB_40M_MASK GENMASK(7, 4)
5898 #define B_BE_RRSR_HE_MASK GENMASK(31, 24)
5901 #define B_BE_RRSR_OFDM_MASK GENMASK(7, 0)
5907 #define B_BE_RSC_MASK GENMASK(7, 6)
5915 #define B_BE_WMAC_TX_ERR_IND_EN BIT(7)
5929 #define B_BE_WMAC_TX_ERR_IND BIT(7)
5940 #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)
5943 #define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0)
5949 #define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0)
5956 #define B_BE_SER_L0_SUBMODULE_BIT31_CNT BIT(31)
5980 #define B_BE_SER_L0_SUBMODULE_BIT7_CNT BIT(7)
5999 #define B_BE_BCNQ_CW_MASK GENMASK(31, 24)
6003 #define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0)
6014 #define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)
6027 #define B_BE_TX_NAV_EN BIT(7)
6068 #define B_BE_TB_CHK_CCA_S160 BIT(7)
6087 #define B_BE_HE_SIFS_CHK_CCA_S160 BIT(7)
6106 #define B_BE_HE_CTN_CHK_CCA_S160 BIT(7)
6138 #define B_BE_BCNERR_CNT_EN_P0 BIT(7)
6150 #define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0)
6177 #define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0)
6181 #define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)
6184 #define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0)
6196 #define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0)
6205 #define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)
6209 #define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)
6213 #define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)
6227 #define B_BE_P0MB7_EN BIT(7)
6244 #define B_BE_MGQ_LIFETIME_EN BIT(7)
6265 #define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6269 #define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)
6273 #define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
6275 #define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)
6279 #define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
6283 #define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
6312 #define B_BE_PTCL_ERROR_FLAG_IMR BIT(31)
6324 #define B_BE_PTCL_ERROR_FLAG_ISR BIT(31)
6397 #define B_BE_PTCL_BUSY BIT(7)
6403 #define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31)
6427 #define B_BE_PLE_DATA_OPT_FSM_HANG BIT(7)
6438 #define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31)
6462 #define B_BE_PLE_DATA_OPT_FSM_HANG_IMR BIT(7)
6526 #define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31)
6547 #define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31)
6674 #define B_BE_TSFT_OFS_MASK GENMASK(31, 16)
6704 #define B_BE_WMAC_RESP_STBC_EN BIT(31)
6718 #define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
6722 #define B_BE_WMAC_RESP_SR_MODE_EN BIT(31)
6738 #define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3)
6749 #define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
6753 #define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)
6768 #define B_BE_RMAC_CSI BIT(7)
6801 #define B_BE_CSI_ERROR_FLAG_CLR BIT(7)
6814 #define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
6818 #define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)
6853 #define B_BE_BFMEE_MU_BFEE_DIS BIT(7)
6880 #define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
6886 #define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)
6895 #define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)
6898 #define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0)
6912 #define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
6932 #define B_BE_ACK_BA_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7)
6952 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
6970 #define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6)
6978 #define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
7000 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
7008 #define B_BE_A_BCN_CHK_EN BIT(7)
7049 #define B_BE_BACAM_SHIFT_POLL BIT(7)
7076 #define B_BE_RX_ERR_CSI_ACT_TO BIT(7)
7089 #define B_BE_RX_ERR_CSI_ACT_TO_MSK BIT(7)
7121 #define B_BE_PLCP_RXSB_SRC BIT(7)
7260 #define RR_CFGCH_CH GENMASK(7, 0)
7283 #define RR_RXK_SEL5G BIT(7)
7287 #define RR_LUTWA_M1 GENMASK(7, 0)
7305 #define RR_TXGA_TRK_EN BIT(7)
7309 #define RR_TXGA_V1_TRK_EN BIT(7)
7344 #define RR_TXPOW_TXAS BIT(7)
7353 #define RR_RXBB_FATT GENMASK(7, 0)
7354 #define RR_RXBB_ATTR GENMASK(7, 4)
7370 #define RR_RXA2_CC2 GENMASK(8, 7)
7371 #define RR_RXA2_IATT GENMASK(7, 4)
7389 #define RR_DCK_DONE GENMASK(7, 5)
7399 #define RR_DCK2_CYCLE GENMASK(7, 2)
7423 #define RR_VCI_ON BIT(7)
7465 #define B_UPD_P0_EN BIT(31)
7472 #define B_ANAPAR_PW15 GENMASK(31, 24)
7476 #define B_ANAPAR_15 GENMASK(31, 16)
7493 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
7497 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
7543 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
7545 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
7552 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
7556 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
7563 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
7568 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
7573 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
7577 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
7581 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
7585 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
7599 #define B_PD_ARBITER_OFF BIT(31)
7631 #define B_P0_RXCK_ADJ GENMASK(31, 23)
7639 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
7649 #define B_S0_RXDC_Q GENMASK(31, 26)
7652 #define B_S0_RXDC2_AVG GENMASK(7, 6)
7661 #define B_EDCCA_RPT_B_FB BIT(7)
7674 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
7678 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
7682 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
7686 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
7689 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
7692 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
7696 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
7700 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
7704 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
7718 #define B_TXAGC_BTP GENMASK(31, 24)
7720 #define B_TXAGC_BB_OFT GENMASK(31, 16)
7721 #define B_TXAGC_BB GENMASK(31, 24)
7731 #define B_ADC_FIFO_RST GENMASK(31, 24)
7732 #define B_ADC_FIFO_RXK GENMASK(31, 16)
7758 #define B_RXCCA_DIS BIT(31)
7786 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
7796 #define B_S1_RXDC_Q GENMASK(31, 26)
7802 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
7803 #define B_TXAGC_BB_S1 GENMASK(31, 24)
7812 #define B_DCFO GENMASK(7, 0)
7832 #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
7834 #define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
7850 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
7896 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
7921 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
7923 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
7939 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
7942 #define B_P1_MODE_SEL GENMASK(31, 30)
7944 #define B_P0_AGC_EN BIT(31)
7957 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
7967 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
7986 #define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
7988 #define B_EDCCA_LVL_MSK0 GENMASK(7, 0)
7996 #define B_FC0_BW_SET GENMASK(31, 30)
8003 #define B_Q_MATRIX_00_REAL GENMASK(31, 16)
8012 #define B_Q_MATRIX_11_REAL GENMASK(31, 16)
8016 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
8021 #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
8023 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
8026 #define B_P0_RTL2_42_MASK GENMASK(7, 0)
8028 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
8031 #define B_P0_RTL3_82_MASK GENMASK(7, 0)
8033 #define B_PD_BOOST_EN BIT(7)
8035 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
8046 #define B_P1_AGC_EN BIT(31)
8051 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
8054 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
8096 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
8102 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
8111 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
8140 #define B_DAC_VAL BIT(31)
8156 #define B_DPD_OFT_ADDR GENMASK(31, 27)
8169 #define B_P0_TSSI_OFT GENMASK(7, 0)
8171 #define B_P0_TSSI_EN BIT(31)
8184 #define B_P0_TRSW_SO_A2 GENMASK(7, 5)
8193 #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
8202 #define B_P0_RFM_DIS_WL BIT(7)
8208 #define B_P0_TXDPD GENMASK(31, 28)
8211 #define B_P0_TXPW_RSTB_TSSI BIT(31)
8218 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
8220 #define B_P0_DAC_COMP_POST_DPD_EN BIT(31)
8223 #define B_S0_DACKI_AR GENMASK(31, 28)
8232 #define B_S0_DACKQ_AR GENMASK(31, 28)
8241 #define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28)
8247 #define B_SEGSND_EN BIT(31)
8249 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
8271 #define B_P1_TSSI_OFT GENMASK(7, 0)
8273 #define B_P1_TSSI_EN BIT(31)
8282 #define B_P1_TXPW_RSTB_TSSI BIT(31)
8288 #define B_P1_DAC_COMP_POST_DPD_EN BIT(31)
8291 #define B_S1_DACKI_AR GENMASK(31, 28)
8300 #define B_S1_DACKQ_AR GENMASK(31, 28)
8313 #define B_NCTL_N1_CIP GENMASK(7, 0)
8334 #define B_MDPK_SYNC_SEL BIT(31)
8335 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
8338 #define B_MDPK_RX_DCK_EN BIT(31)
8365 #define B_IDL_DN BIT(31)
8378 #define B_DPK_TRK_DIS BIT(31)
8386 #define B_PRT_COM_GL GENMASK(7, 4)
8387 #define B_PRT_COM_CORI GENMASK(7, 0)
8404 #define B_RXIQC_NEWX GENMASK(31, 20)
8425 #define B_DPD_LBK BIT(7)
8431 #define B_DPD_MEN GENMASK(31, 28)
8452 #define B_DPK_GL_A0 GENMASK(31, 28)
8455 #define B_RPT_PER_KSET GENMASK(31, 29)
8479 #define B_IQKINF_VER GENMASK(31, 24)
8489 #define B_IQKCH_BW GENMASK(7, 4)
8494 #define B_IQKINF2_NCTLV GENMASK(7, 0)
8506 #define B_DACK_S0P0_OK BIT(31)
8510 #define B_DACK_S0M0 GENMASK(31, 24)
8513 #define B_DACK_DADCK00 GENMASK(31, 24)
8515 #define B_DACK_S0P1_OK BIT(31)
8519 #define B_DACK_S0M1 GENMASK(31, 24)
8522 #define B_DACK_DADCK01 GENMASK(31, 24)
8545 #define B_P0_CFCH_CTL GENMASK(10, 7)
8552 #define B_ADCMOD_LP GENMASK(31, 16)
8556 #define B_ADDCK0D_VAL2 GENMASK(31, 26)
8582 #define B_DACK_S1P0_OK BIT(31)
8586 #define B_DACK10S GENMASK(31, 24)
8590 #define B_DACK_DADCK10 GENMASK(31, 24)
8592 #define B_DACK_S1P1_OK BIT(31)
8596 #define B_DACK11S GENMASK(31, 24)
8600 #define B_DACK_DADCK11 GENMASK(31, 24)
8609 #define B_ADDCK1D_VAL2 GENMASK(31, 26)
8632 #define B_AX_WDT_EN BIT(31)