Lines Matching +full:4 +full:- +full:31

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
22 #define B_AX_SOP_ASWRM BIT(31)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
70 #define B_AX_EF_ENT BIT(31)
98 #define B_AX_EROM_EN BIT(4)
103 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
125 #define B_AX_FORCED_IB_EN BIT(4)
146 #define B_AX_TOGGLE BIT(31)
154 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
169 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
181 #define MAC_AX_HCI_SEL_MULTI_SDIO 4
212 #define B_AX_EN_32K BIT(31)
216 #define B_AX_UDM1_MASK GENMASK(31, 16)
219 #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
239 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
254 #define B_AX_XTAL_SC_LPS BIT(31)
268 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
271 #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
298 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
303 #define B_AX_C3_L1_MASK GENMASK(5, 4)
317 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
330 #define B_AX_FLUSH_AXI_MST BIT(4)
392 #define B_AX_LTR_DRV_DEC_EN BIT(4)
488 #define B_AX_DMAC_CRPRT BIT(31)
525 #define PCI_LTR_IDLE_TIMER_400US 4
546 #define B_AX_APP_LTR_IDLE BIT(4)
560 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
578 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
591 #define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
604 #define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
609 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
623 #define B_AX_WDE_DLE_ERR_FLAG BIT(4)
639 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
664 #define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
704 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
729 #define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
771 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
795 #define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
856 #define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
909 #define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
933 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
997 #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
1007 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
1018 #define B_AX_GRP BIT(31)
1082 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1085 #define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
1108 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1169 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1238 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
1257 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1264 #define B_AX_WDE_DFI_ACTIVE BIT(31)
1268 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1279 #define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
1289 #define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
1296 #define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
1304 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1312 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1323 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
1344 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1394 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1472 #define B_AX_PLE_DFI_ACTIVE BIT(31)
1476 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1498 #define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
1546 #define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
1556 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1582 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1612 #define B_AX_WD_BUF_REQ_EXEC BIT(31)
1618 #define B_AX_WD_BUF_STAT_DONE BIT(31)
1624 #define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1643 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1649 #define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
1679 #define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
1728 #define B_AX_UC_MGNT_DEC BIT(4)
1746 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1768 #define B_AX_SS_INIT_DONE_1 BIT(31)
1774 #define B_AX_SS_UL_REL BIT(31)
1783 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1787 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1791 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1795 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1846 #define B_AX_DFI_ACTIVE BIT(31)
1850 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1853 #define B_AX_B0_PRELD_FEN BIT(31)
1858 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1917 #define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
1924 #define B_AX_B1_PRELD_FEN BIT(31)
1926 #define PRELD_B1_ENT_NUM 4
1928 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1986 #define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
1994 #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
2010 #define B_AX_CMAC_CRPRT BIT(31)
2016 #define B_AX_CMAC_DMA_EN BIT(4)
2024 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2027 #define B_AX_CMAC_DMA_CKEN BIT(4)
2057 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2072 #define B_AX_PHYINTF_ERR_IND_EN BIT(4)
2076 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2077 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2086 #define B_AX_PHYINTF_ERR_IND BIT(4)
2111 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2116 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2121 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2126 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2131 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2146 #define B_AX_EDCCA_EN BIT(4)
2165 #define B_AX_CTN_TXEN_BE_1 BIT(4)
2174 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2188 #define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
2193 #define B_AX_TB_CHK_TX_NAV BIT(31)
2211 #define B_AX_CTN_CHK_EDCCA BIT(4)
2238 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2260 #define B_AX_RX_BSSID_FIT_EN BIT(4)
2325 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2337 #define B_AX_BCN_ERR_FLAG_TXON BIT(4)
2365 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2372 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2379 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2383 #define B_AX_BCN_DROP_ALL_P4 BIT(4)
2404 #define B_AX_P0MB4_EN BIT(4)
2420 #define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
2427 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2434 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2441 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2447 #define S_AX_CTS2S_TH_1K 4
2452 #define B_AX_BAND_MODE BIT(4)
2459 #define B_AX_ADD_TXCNT_BY BIT(31)
2476 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2484 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2490 #define B_AX_RX_PLT_GNT_WL BIT(4)
2509 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2527 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2574 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2596 #define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
2623 #define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
2631 #define B_AX_RXDMA_DBGOUT_EN BIT(31)
2642 #define B_AX_CSI_PTR_FULL_MODE BIT(4)
2653 #define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
2665 #define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
2670 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
2677 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2684 #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2692 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2726 #define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4)
2784 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2825 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2835 #define B_AX_TCR_EN_EOF BIT(4)
2843 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2856 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2872 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2877 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2891 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2895 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2912 #define B_AX_WMAC_RESP_STBC_EN BIT(31)
2934 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
2963 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2978 #define B_AX_TMAC_HWSIGB_GEN BIT(4)
3007 #define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
3019 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3023 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3058 #define B_AX_STS_ON_TIMEOUT_EN BIT(4)
3103 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3111 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3169 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3176 #define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
3184 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3198 #define B_AX_A_UC_CAM_MATCH BIT(4)
3239 #define B_AX_PPDU_STAT_RPT_A1M BIT(4)
3256 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3257 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3260 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3264 #define B_AX_RXERR_INTPS_EN BIT(31)
3276 #define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
3301 #define B_AX_DATAON_ASSERT_TO_MSK BIT(4)
3329 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3330 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3379 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3381 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3383 #define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)
3385 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3387 #define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)
3415 #define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28)
3421 #define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4)
3454 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3463 #define B_AX_BTC_EN BIT(31)
3474 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3529 #define MAC_AX_CSR_TRX_TO 4
3530 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3540 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3544 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3565 #define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4)
3573 #define B_AX_GNT_WL_RFC_S1_STA BIT(4)
3578 #define B_AX_GNT_BT_RFC_S1 BIT(4)
3585 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3589 #define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
3597 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3614 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3636 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3646 #define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
3664 #define B_BE_ISO_PD2CORE BIT(4)
3670 #define B_BE_SOP_ASWRM BIT(31)
3714 #define B_BE_AUTOLOAD_DIS BIT(4)
3739 #define B_BE_DIS_CLK_REG4_GATE BIT(4)
3756 #define B_BE_FORCE_MACBBBT_PWR_ON BIT(31)
3777 #define B_BE_R_SYM_WLBBOFF_P4_PC_EN BIT(4)
3805 #define B_BE_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
3817 #define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
3823 #define B_BE_EF_DATA_MASK GENMASK(31, 0)
3826 #define B_BE_ISO_BD2PP BIT(31)
3843 #define B_BE_DOP_EHPAD BIT(4)
3868 #define B_BE_USB_D_STATE_HOLD BIT(4)
3875 #define B_BE_HCI_WLAN_IO_ST BIT(31)
3897 #define B_BE_USB_LPPLL_EN BIT(4)
3922 #define B_BE_R_SYM_ISO_HCILA BIT(4)
3928 #define B_BE_R_SYM_FEN_WLMACOFF BIT(31)
3944 #define B_BE_SYM_ISO_BB02PP BIT(4)
3957 #define B_BE_HIOE_EN BIT(4)
3978 #define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4)
3985 #define B_BE_LPSROP_DMEM5_RSU_EN BIT(31)
4005 #define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4)
4008 #define B_BE_EF_ENT BIT(31)
4024 #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
4031 #define B_BE_R_BE_RST_PD12N BIT(4)
4046 #define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4055 #define B_BE_HALT_H2C_MASK GENMASK(31, 0)
4058 #define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28)
4088 #define B_BE_FS_GPIO20_INT_EN BIT(4)
4115 #define B_BE_GPIO4_INT_EN BIT(4)
4142 #define B_BE_GPIO4_INT BIT(4)
4149 #define B_BE_RUN_ENV_MASK GENMASK(31, 30)
4159 #define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4)
4168 #define B_BE_EN_32K BIT(31)
4172 #define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28)
4178 #define B_BE_FW_IMAGE_TYPE BIT(4)
4184 #define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16)
4187 #define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
4191 #define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4194 #define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
4202 #define B_BE_REG_IB_PI_MASK GENMASK(5, 4)
4208 #define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29)
4221 #define B_BE_REG_LPF_C1_FAST_MASK GENMASK(4, 2)
4225 #define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30)
4240 #define B_BE_REG_09LDO_SEL_MASK GENMASK(5, 4)
4247 #define B_BE_WL_XTAL_SI_CMD_POLL BIT(31)
4259 #define B_BE_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
4277 #define B_BE_PL_AXIDMA_FC_ERR_MASK BIT(4)
4296 #define B_BE_PL_AXIDMA_FC_ERR BIT(4)
4305 #define B_BE_WLAN_WDT_TIMEOUT BIT(31)
4306 #define B_BE_WLAN_WDT_TIMER_CLEAR BIT(4)
4311 #define B_BE_AXIDMA_WDT_TIMEOUT BIT(31)
4312 #define B_BE_AXIDMA_WDT_TIMER_CLEAR BIT(4)
4317 #define B_BE_AON_WDT_TIMEOUT BIT(31)
4318 #define B_BE_AON_WDT_TIMER_CLEAR BIT(4)
4335 #define B_BE_LOCAL_WDT_TIMEOUT BIT(31)
4336 #define B_BE_LOCAL_WDT_TIMER_CLEAR BIT(4)
4341 #define B_BE_MDIO_WDT_TIMEOUT BIT(31)
4342 #define B_BE_MDIO_WDT_TIMER_CLEAR BIT(4)
4347 #define B_BE_LA_MODE_WDT_TIMEOUT BIT(31)
4348 #define B_BE_LA_MODE_WDT_TIMER_CLEAR BIT(4)
4353 #define B_BE_WDT_AR_TIMEOUT BIT(31)
4354 #define B_BE_WDT_AR_TIMER_CLEAR BIT(4)
4359 #define B_BE_WDT_AW_TIMEOUT BIT(31)
4360 #define B_BE_WDT_AW_TIMER_CLEAR BIT(4)
4365 #define B_BE_WDT_W_TIMEOUT BIT(31)
4366 #define B_BE_WDT_W_TIMER_CLEAR BIT(4)
4371 #define B_BE_WDT_B_TIMEOUT BIT(31)
4372 #define B_BE_WDT_B_TIMER_CLEAR BIT(4)
4377 #define B_BE_WDT_R_TIMEOUT BIT(31)
4378 #define B_BE_WDT_R_TIMER_CLEAR BIT(4)
4383 #define B_BE_ENABLE_LTR_CTL_DECISION BIT(31)
4393 #define B_BE_LTR_EN_PORT_V1_MASK GENMASK(6, 4)
4396 #define B_BE_LTR_HW_DEC_EN_V1 BIT(4)
4405 #define B_BE_HCI_CR_PROTECT BIT(31)
4411 #define B_BE_DMAC_CRPRT BIT(31)
4479 #define B_BE_HWAMSDU_PADDING_MODE BIT(31)
4486 #define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)
4515 #define B_BE_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
4529 #define B_BE_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
4536 #define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)
4542 #define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)
4548 #define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)
4554 #define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)
4560 #define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)
4564 #define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)
4567 #define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)
4570 #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)
4589 #define B_BE_WDE_DLE_ERR_INT_EN BIT(4)
4610 #define B_BE_WDE_DLE_ERR_FLAG BIT(4)
4617 #define B_BE_REUSE_SIZE_ERR BIT(31)
4642 #define B_BE_WDE_OUTPUT_ERR BIT(4)
4649 #define B_BE_HR_WRFF_UNDERFLOW_ERR BIT(31)
4673 #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4703 #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4709 #define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31)
4734 #define B_BE_WDE_OUTPUT_ERR_INT_EN BIT(4)
4777 #define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
4801 #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
4878 #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
4928 #define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)
4941 #define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4)
4974 #define B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5090 #define B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5216 #define B_BE_PLE_DFI_ACTIVE BIT(31)
5221 #define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
5224 #define B_BE_WDRLS_DIS_AGAC BIT(31)
5239 #define B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
5265 #define S_BE_WDRLS_FLTR_LIFTIM 4
5305 #define B_BE_CHIF_BBONL_BFACT_ISR_EN BIT(4)
5321 #define B_BE_WD_BUF_REQ_EXEC BIT(31)
5326 #define B_BE_WD_BUF_STAT_DONE BIT(31)
5330 #define B_BE_WD_CPUQ_OP_EXEC BIT(31)
5336 #define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5341 #define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5349 #define B_BE_WD_CPUQ_OP_STAT_DONE BIT(31)
5354 #define B_BE_PL_BUF_REQ_EXEC BIT(31)
5359 #define B_BE_PL_BUF_STAT_DONE BIT(31)
5363 #define B_BE_PL_CPUQ_OP_EXEC BIT(31)
5369 #define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5374 #define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5382 #define B_BE_PL_CPUQ_OP_STAT_DONE BIT(31)
5389 #define B_BE_WDEQUE_OP_ERR_INT_EN BIT(4)
5409 #define B_BE_TX_ADDR_MLD_TO_LIK BIT(4)
5427 #define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4)
5433 #define B_BE_EN_CUT_AMSDU BIT(31)
5442 #define B_BE_HDR_INFO_MASK GENMASK(5, 4)
5456 #define B_BE_SEC_ENG_EN BIT(31)
5474 #define B_BE_UC_MGNT_DEC BIT(4)
5485 #define B_BE_RESP1_PROTECT BIT(4)
5492 #define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16)
5499 #define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)
5502 #define B_BE_DBG_READ_MASK GENMASK(31, 0)
5505 #define B_BE_QUEUE_OPERATION_HANG_IMR BIT(4)
5523 #define B_BE_QUEUE_OPERATION_HANG_ERROR BIT(4)
5530 #define B_BE_MPDUINFO_FEN BIT(31)
5536 #define B_BE_B0_PRELD_FEN BIT(31)
5539 #define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5576 #define B_BE_B1_PRELD_FEN BIT(31)
5579 #define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5616 #define B_BE_MLO_TABLE_INIT_DONE BIT(31)
5622 #define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31)
5634 #define B_BE_MLO_ISR_IDCT_0 BIT(31)
5651 #define B_BE_SS_INIT_DONE BIT(31)
5669 #define B_BE_AVG_INIT_EN BIT(4)
5691 #define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
5708 #define B_BE_TXDMA_EN BIT(4)
5713 #define B_BE_STOP_WPDMA BIT(31)
5724 #define B_BE_STOP_CH4 BIT(4)
5734 #define B_BE_SET_FC_ERROR_FLAG_IDCT_MSK BIT(4)
5758 #define B_BE_SET_FC_ERROR_FLAG_IDCT BIT(4)
5771 #define B_BE_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
5809 #define B_BE_CMAC_SHARE_CRPRT BIT(31)
5819 #define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)
5820 #define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4)
5827 #define B_BE_CMAC_CRPRT BIT(31)
5846 #define B_BE_CMAC_DMA_EN BIT(4)
5866 #define B_BE_CMAC_DMA_CKEN BIT(4)
5878 #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)
5886 #define S_BE_TXSB_80M_4 4
5887 #define B_BE_TXSB_40M_MASK GENMASK(7, 4)
5890 #define S_BE_TXSB_40M_4 4
5893 #define S_BE_TXSB_20M_4 4
5898 #define B_BE_RRSR_HE_MASK GENMASK(31, 24)
5918 #define B_BE_PHYINTF_ERR_IND_EN BIT(4)
5932 #define B_BE_PHYINTF_ERR_IND BIT(4)
5940 #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)
5956 #define B_BE_SER_L0_SUBMODULE_BIT31_CNT BIT(31)
5983 #define B_BE_SER_L0_SUBMODULE_BIT4_CNT BIT(4)
5999 #define B_BE_BCNQ_CW_MASK GENMASK(31, 24)
6010 #define B_BE_PREBKF_TIME_MASK GENMASK(4, 0)
6014 #define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)
6030 #define B_BE_EDCCA_EN BIT(4)
6055 #define B_BE_SET_MUEDCATIMER_TF_0 BIT(4)
6071 #define B_BE_TB_CHK_CCA_S20 BIT(4)
6090 #define B_BE_HE_SIFS_CHK_CCA_S20 BIT(4)
6109 #define B_BE_HE_CTN_CHK_CCA_S20 BIT(4)
6141 #define B_BE_RX_BSSID_FIT_EN_P0 BIT(4)
6181 #define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)
6205 #define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)
6209 #define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)
6213 #define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)
6230 #define B_BE_P0MB4_EN BIT(4)
6247 #define B_BE_PTCL_TRIGGER_SS_EN_UL BIT(4)
6265 #define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6273 #define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
6279 #define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
6312 #define B_BE_PTCL_ERROR_FLAG_IMR BIT(31)
6324 #define B_BE_PTCL_ERROR_FLAG_ISR BIT(31)
6399 #define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0)
6403 #define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31)
6430 #define B_BE_PLE_WD_OPT_FSM_HANG BIT(4)
6438 #define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31)
6465 #define B_BE_PLE_WD_OPT_FSM_HANG_IMR BIT(4)
6526 #define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31)
6547 #define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31)
6674 #define B_BE_TSFT_OFS_MASK GENMASK(31, 16)
6686 #define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0)
6704 #define B_BE_WMAC_RESP_STBC_EN BIT(31)
6722 #define B_BE_WMAC_RESP_SR_MODE_EN BIT(31)
6753 #define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)
6771 #define B_BE_TMAC_HWSIGB_GEN BIT(4)
6804 #define B_BE_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
6818 #define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)
6824 #define B_BE_STS_ON_TIMEOUT_EN BIT(4)
6840 #define B_BE_STS_ON_TIMEOUT_ERR BIT(4)
6856 #define B_BE_BFMEE_VHTBFRPT_CHK BIT(4)
6886 #define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)
6895 #define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)
6915 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
6935 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA80 BIT(4)
6955 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4)
6971 #define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4)
6978 #define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
6992 #define B_BE_VHT_SU_SIGB_CRC_CHK BIT(4)
7000 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
7011 #define B_BE_A_UC_CAM_MATCH BIT(4)
7061 #define B_BE_SR_OP_MODE_MASK GENMASK(5, 4)
7079 #define B_BE_DATAON_ASSERT_TO BIT(4)
7092 #define B_BE_DATAON_ASSERT_TO_MSK BIT(4)
7123 #define B_BE_PLCP_GILTF_SRC BIT(4)
7148 #define B_BE_RESP_TXCMD_TBL_ERR_ISR_EN BIT(4)
7206 #define RR_MOD_IQK GENMASK(19, 4)
7210 #define RR_MOD_RGM GENMASK(13, 4)
7222 #define RR_MOD_M_RXG GENMASK(13, 4)
7237 #define RR_LOKVB_COQ GENMASK(9, 4)
7240 #define RR_TXIG_GR1 GENMASK(6, 4)
7266 #define RR_APK_MOD GENMASK(5, 4)
7288 #define RR_LUTWA_M2 GENMASK(4, 0)
7306 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
7313 #define RR_GAINTX_BB GENMASK(4, 0)
7332 #define RR_BIASA2_LB GENMASK(4, 2)
7354 #define RR_RXBB_ATTR GENMASK(7, 4)
7371 #define RR_RXA2_IATT GENMASK(7, 4)
7410 #define RR_MIXER_GN GENMASK(4, 3)
7417 #define RR_IBD_VAL GENMASK(4, 0)
7435 #define RR_LCK_ST BIT(4)
7442 #define RR_SYNLUT_MOD BIT(4)
7465 #define B_UPD_P0_EN BIT(31)
7472 #define B_ANAPAR_PW15 GENMASK(31, 24)
7476 #define B_ANAPAR_15 GENMASK(31, 16)
7493 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
7543 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
7545 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
7548 #define B_MAC_SEL_MOD GENMASK(4, 2)
7552 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
7554 #define B_PMAC_PTX_EN BIT(4)
7556 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
7562 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
7563 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
7568 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
7573 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
7577 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
7581 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
7585 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
7597 #define B_TXGATING_EN BIT(4)
7599 #define B_PD_ARBITER_OFF BIT(31)
7631 #define B_P0_RXCK_ADJ GENMASK(31, 23)
7639 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
7640 #define B_P0_RFMODE_MUX GENMASK(11, 4)
7649 #define B_S0_RXDC_Q GENMASK(31, 26)
7653 #define B_S0_RXDC2_MEN GENMASK(5, 4)
7664 #define B_EDCCA_RPT_B_S40 BIT(4)
7674 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
7678 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
7682 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
7686 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
7692 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
7696 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
7700 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
7704 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
7718 #define B_TXAGC_BTP GENMASK(31, 24)
7720 #define B_TXAGC_BB_OFT GENMASK(31, 16)
7721 #define B_TXAGC_BB GENMASK(31, 24)
7731 #define B_ADC_FIFO_RST GENMASK(31, 24)
7732 #define B_ADC_FIFO_RXK GENMASK(31, 16)
7758 #define B_RXCCA_DIS BIT(31)
7786 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
7787 #define B_P1_RFMODE_MUX GENMASK(11, 4)
7796 #define B_S1_RXDC_Q GENMASK(31, 26)
7798 #define B_S1_RXDC2_EN GENMASK(5, 4)
7802 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
7803 #define B_TXAGC_BB_S1 GENMASK(31, 24)
7832 #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
7834 #define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
7850 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
7896 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
7921 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
7939 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
7942 #define B_P1_MODE_SEL GENMASK(31, 30)
7944 #define B_P0_AGC_EN BIT(31)
7957 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
7986 #define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
7996 #define B_FC0_BW_SET GENMASK(31, 30)
8003 #define B_Q_MATRIX_00_REAL GENMASK(31, 16)
8012 #define B_Q_MATRIX_11_REAL GENMASK(31, 16)
8016 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
8023 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
8028 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
8035 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
8046 #define B_P1_AGC_EN BIT(31)
8051 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
8054 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
8111 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
8140 #define B_DAC_VAL BIT(31)
8156 #define B_DPD_OFT_ADDR GENMASK(31, 27)
8171 #define B_P0_TSSI_EN BIT(31)
8193 #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
8205 #define B_P0_RFM_OUT GENMASK(4, 0)
8208 #define B_P0_TXDPD GENMASK(31, 28)
8211 #define B_P0_TXPW_RSTB_TSSI BIT(31)
8218 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
8220 #define B_P0_DAC_COMP_POST_DPD_EN BIT(31)
8223 #define B_S0_DACKI_AR GENMASK(31, 28)
8232 #define B_S0_DACKQ_AR GENMASK(31, 28)
8241 #define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28)
8247 #define B_SEGSND_EN BIT(31)
8273 #define B_P1_TSSI_EN BIT(31)
8282 #define B_P1_TXPW_RSTB_TSSI BIT(31)
8288 #define B_P1_DAC_COMP_POST_DPD_EN BIT(31)
8291 #define B_S1_DACKI_AR GENMASK(31, 28)
8300 #define B_S1_DACKQ_AR GENMASK(31, 28)
8327 #define B_IQK_CFG_SET GENMASK(5, 4)
8334 #define B_MDPK_SYNC_SEL BIT(31)
8335 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
8338 #define B_MDPK_RX_DCK_EN BIT(31)
8365 #define B_IDL_DN BIT(31)
8378 #define B_DPK_TRK_DIS BIT(31)
8386 #define B_PRT_COM_GL GENMASK(7, 4)
8389 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
8404 #define B_RXIQC_NEWX GENMASK(31, 20)
8409 #define B_RFGAIN_PAD GENMASK(4, 0)
8412 #define B_RFGAIN_BND GENMASK(4, 0)
8416 #define B_CFIR_LUT_SET BIT(4)
8431 #define B_DPD_MEN GENMASK(31, 28)
8452 #define B_DPK_GL_A0 GENMASK(31, 28)
8455 #define B_RPT_PER_KSET GENMASK(31, 29)
8479 #define B_IQKINF_VER GENMASK(31, 24)
8489 #define B_IQKCH_BW GENMASK(7, 4)
8497 #define B_DCOF0_V GENMASK(4, 1)
8502 #define B_DCOF8_V GENMASK(4, 1)
8506 #define B_DACK_S0P0_OK BIT(31)
8510 #define B_DACK_S0M0 GENMASK(31, 24)
8513 #define B_DACK_DADCK00 GENMASK(31, 24)
8515 #define B_DACK_S0P1_OK BIT(31)
8519 #define B_DACK_S0M1 GENMASK(31, 24)
8522 #define B_DACK_DADCK01 GENMASK(31, 24)
8529 #define B_DRCK_VAL GENMASK(4, 0)
8536 #define B_DRCK_V1_CV GENMASK(4, 0)
8550 #define B_WDADC_SEL GENMASK(5, 4)
8552 #define B_ADCMOD_LP GENMASK(31, 16)
8556 #define B_ADDCK0D_VAL2 GENMASK(31, 26)
8563 #define B_ADDCK0_MAN GENMASK(5, 4)
8564 #define B_ADDCK0_EN BIT(4)
8573 #define B_ADDCKR0_DC GENMASK(15, 4)
8576 #define B_DACK10 GENMASK(4, 1)
8580 #define B_DACK11 GENMASK(4, 1)
8582 #define B_DACK_S1P0_OK BIT(31)
8586 #define B_DACK10S GENMASK(31, 24)
8590 #define B_DACK_DADCK10 GENMASK(31, 24)
8592 #define B_DACK_S1P1_OK BIT(31)
8596 #define B_DACK11S GENMASK(31, 24)
8600 #define B_DACK_DADCK11 GENMASK(31, 24)
8609 #define B_ADDCK1D_VAL2 GENMASK(31, 26)
8614 #define B_ADDCK1_MAN GENMASK(5, 4)
8615 #define B_ADDCK1_EN BIT(4)
8632 #define B_AX_WDT_EN BIT(31)