Lines Matching +full:0 +full:x1032
10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA0A 0x0A
17 #define RAC_ANA0C 0x0C
19 #define RAC_ANA10 0x10
21 #define RAC_REG_REV2 0x1B
23 #define PCIE_DPHY_DLY_25US 0x1
24 #define RAC_ANA19 0x19
26 #define RAC_REG_FLD_0 0x1D
28 #define PCIE_AUTOK_4 0x3
29 #define RAC_ANA1F 0x1F
30 #define RAC_ANA24 0x24
32 #define RAC_ANA26 0x26
34 #define RAC_CTRL_PPR_V1 0x30
38 #define RAC_SET_PPR_V1 0x31
40 #define R_AX_DBI_FLAG 0x1090
45 #define R_AX_DBI_WDATA 0x1094
46 #define R_AX_DBI_RDATA 0x1098
48 #define R_AX_MDIO_WDATA 0x10A4
49 #define R_AX_MDIO_RDATA 0x10A6
51 #define R_AX_PCIE_PS_CTRL_V1 0x3008
56 #define B_AX_SEL_REQ_EXIT_L1 BIT(0)
58 #define R_AX_PCIE_MIX_CFG_V1 0x300C
66 #define B_AX_L1SUB_DISABLE BIT(0)
68 #define R_AX_L1_CLK_CTRL 0x3010
71 #define R_AX_PCIE_BG_CLR 0x303C
74 #define R_AX_PCIE_LAT_CTRL 0x3044
76 #define B_AX_CLK_REQ_SEL BIT(0)
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
126 #define R_AX_HIMR0 0x01A0
129 #define R_AX_HISR0 0x01A4
131 #define R_AX_HIMR1 0x01A8
134 #define B_AX_GPIO16_INT_EN BIT(0)
136 #define R_AX_HISR1 0x01AC
139 #define B_AX_GPIO16_INT BIT(0)
141 #define R_AX_MDIO_CFG 0x10A0
145 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
147 #define R_AX_PCIE_HIMR00 0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
175 #define B_AX_RXDMA_INT_EN BIT(0)
177 #define R_AX_PCIE_HISR00 0x10B4
178 #define R_AX_HAXI_HISR00 0x10B4
204 #define B_AX_RXDMA_INT BIT(0)
206 #define R_AX_HAXI_IDCT_MSK 0x10B8
210 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
212 #define R_AX_HAXI_IDCT 0x10BC
216 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
218 #define R_AX_HAXI_HIMR10 0x11E0
220 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
222 #define R_AX_PCIE_HIMR10 0x13B0
227 #define R_AX_PCIE_HISR10 0x13B4
232 #define R_AX_PCIE_HIMR00_V1 0x30B0
240 #define R_AX_PCIE_HISR00_V1 0x30B4
248 #define R_BE_PCIE_FRZ_CLK 0x3004
271 #define B_BE_PCIE_EN_AUX_CLK BIT(0)
273 #define R_BE_PCIE_PS_CTRL 0x3008
282 #define B_BE_SEL_REQ_EXIT_L1 BIT(0)
284 #define R_BE_PCIE_LAT_CTRL 0x3044
293 #define R_BE_PCIE_HIMR0 0x30B0
314 #define B_BE_HS0_IND_INT_EN0 BIT(0)
316 #define R_BE_PCIE_HISR 0x30B4
329 #define B_BE_HS0ISR_IND_INT BIT(0)
331 #define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
354 #define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
356 #define R_BE_PCIE_DMA_ISR 0x30BC
379 #define B_BE_PCIE_TX_CH0_ISR BIT(0)
381 #define R_BE_HAXI_HIMR00 0xB0B0
412 #define B_BE_RX0DMA_INT_EN BIT(0)
414 #define R_BE_HAXI_HISR00 0xB0B4
443 #define B_BE_RX0DMA_INT BIT(0)
446 #define R_AX_DRV_FW_HSK_0 0x01B0
447 #define R_AX_DRV_FW_HSK_1 0x01B4
448 #define R_AX_DRV_FW_HSK_2 0x01B8
449 #define R_AX_DRV_FW_HSK_3 0x01BC
450 #define R_AX_DRV_FW_HSK_4 0x01C0
451 #define R_AX_DRV_FW_HSK_5 0x01C4
452 #define R_AX_DRV_FW_HSK_6 0x01C8
453 #define R_AX_DRV_FW_HSK_7 0x01CC
455 #define R_AX_RXQ_RXBD_IDX 0x1050
456 #define R_AX_RPQ_RXBD_IDX 0x1054
457 #define R_AX_ACH0_TXBD_IDX 0x1058
458 #define R_AX_ACH1_TXBD_IDX 0x105C
459 #define R_AX_ACH2_TXBD_IDX 0x1060
460 #define R_AX_ACH3_TXBD_IDX 0x1064
461 #define R_AX_ACH4_TXBD_IDX 0x1068
462 #define R_AX_ACH5_TXBD_IDX 0x106C
463 #define R_AX_ACH6_TXBD_IDX 0x1070
464 #define R_AX_ACH7_TXBD_IDX 0x1074
465 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
466 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
467 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
468 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
469 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
470 #define R_AX_CH10_TXBD_IDX_V1 0x11D0
471 #define R_AX_CH11_TXBD_IDX_V1 0x11D4
472 #define R_AX_RXQ_RXBD_IDX_V1 0x1218
473 #define R_AX_RPQ_RXBD_IDX_V1 0x121C
475 #define TXBD_HOST_IDX_MASK GENMASK(11, 0)
477 #define R_AX_ACH0_TXBD_DESA_L 0x1110
478 #define R_AX_ACH0_TXBD_DESA_H 0x1114
479 #define R_AX_ACH1_TXBD_DESA_L 0x1118
480 #define R_AX_ACH1_TXBD_DESA_H 0x111C
481 #define R_AX_ACH2_TXBD_DESA_L 0x1120
482 #define R_AX_ACH2_TXBD_DESA_H 0x1124
483 #define R_AX_ACH3_TXBD_DESA_L 0x1128
484 #define R_AX_ACH3_TXBD_DESA_H 0x112C
485 #define R_AX_ACH4_TXBD_DESA_L 0x1130
486 #define R_AX_ACH4_TXBD_DESA_H 0x1134
487 #define R_AX_ACH5_TXBD_DESA_L 0x1138
488 #define R_AX_ACH5_TXBD_DESA_H 0x113C
489 #define R_AX_ACH6_TXBD_DESA_L 0x1140
490 #define R_AX_ACH6_TXBD_DESA_H 0x1144
491 #define R_AX_ACH7_TXBD_DESA_L 0x1148
492 #define R_AX_ACH7_TXBD_DESA_H 0x114C
493 #define R_AX_CH8_TXBD_DESA_L 0x1150
494 #define R_AX_CH8_TXBD_DESA_H 0x1154
495 #define R_AX_CH9_TXBD_DESA_L 0x1158
496 #define R_AX_CH9_TXBD_DESA_H 0x115C
497 #define R_AX_CH10_TXBD_DESA_L 0x1358
498 #define R_AX_CH10_TXBD_DESA_H 0x135C
499 #define R_AX_CH11_TXBD_DESA_L 0x1360
500 #define R_AX_CH11_TXBD_DESA_H 0x1364
501 #define R_AX_CH12_TXBD_DESA_L 0x1160
502 #define R_AX_CH12_TXBD_DESA_H 0x1164
503 #define R_AX_RXQ_RXBD_DESA_L 0x1100
504 #define R_AX_RXQ_RXBD_DESA_H 0x1104
505 #define R_AX_RPQ_RXBD_DESA_L 0x1108
506 #define R_AX_RPQ_RXBD_DESA_H 0x110C
507 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
508 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
509 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
510 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
511 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
512 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
513 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
514 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
515 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
516 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
517 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
518 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
519 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
520 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
521 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
522 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
523 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
524 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
525 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
526 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
527 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
528 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
529 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
530 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
531 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
532 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
533 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
534 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
535 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
536 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
537 #define B_AX_DESC_NUM_MSK GENMASK(11, 0)
539 #define R_AX_RXQ_RXBD_NUM 0x1020
540 #define R_AX_RPQ_RXBD_NUM 0x1022
541 #define R_AX_ACH0_TXBD_NUM 0x1024
542 #define R_AX_ACH1_TXBD_NUM 0x1026
543 #define R_AX_ACH2_TXBD_NUM 0x1028
544 #define R_AX_ACH3_TXBD_NUM 0x102A
545 #define R_AX_ACH4_TXBD_NUM 0x102C
546 #define R_AX_ACH5_TXBD_NUM 0x102E
547 #define R_AX_ACH6_TXBD_NUM 0x1030
548 #define R_AX_ACH7_TXBD_NUM 0x1032
549 #define R_AX_CH8_TXBD_NUM 0x1034
550 #define R_AX_CH9_TXBD_NUM 0x1036
551 #define R_AX_CH10_TXBD_NUM 0x1338
552 #define R_AX_CH11_TXBD_NUM 0x133A
553 #define R_AX_CH12_TXBD_NUM 0x1038
554 #define R_AX_RXQ_RXBD_NUM_V1 0x1210
555 #define R_AX_RPQ_RXBD_NUM_V1 0x1212
556 #define R_AX_CH10_TXBD_NUM_V1 0x1438
557 #define R_AX_CH11_TXBD_NUM_V1 0x143A
559 #define R_AX_ACH0_BDRAM_CTRL 0x1200
560 #define R_AX_ACH1_BDRAM_CTRL 0x1204
561 #define R_AX_ACH2_BDRAM_CTRL 0x1208
562 #define R_AX_ACH3_BDRAM_CTRL 0x120C
563 #define R_AX_ACH4_BDRAM_CTRL 0x1210
564 #define R_AX_ACH5_BDRAM_CTRL 0x1214
565 #define R_AX_ACH6_BDRAM_CTRL 0x1218
566 #define R_AX_ACH7_BDRAM_CTRL 0x121C
567 #define R_AX_CH8_BDRAM_CTRL 0x1220
568 #define R_AX_CH9_BDRAM_CTRL 0x1224
569 #define R_AX_CH10_BDRAM_CTRL 0x1320
570 #define R_AX_CH11_BDRAM_CTRL 0x1324
571 #define R_AX_CH12_BDRAM_CTRL 0x1228
572 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
573 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
574 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
575 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
576 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
577 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
578 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
579 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
580 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
581 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
582 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
583 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
584 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
585 #define BDRAM_SIDX_MASK GENMASK(7, 0)
589 #define R_AX_PCIE_INIT_CFG1 0x1000
606 #define R_AX_TXDMA_ADDR_H 0x10F0
607 #define R_AX_RXDMA_ADDR_H 0x10F4
609 #define R_AX_PCIE_DMA_STOP1 0x1010
624 #define B_AX_STOP_RXQ BIT(0)
637 #define R_AX_PCIE_DMA_STOP2 0x1310
639 #define B_AX_STOP_CH10 BIT(0)
640 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
642 #define R_AX_TXBD_RWPTR_CLR1 0x1014
653 #define B_AX_CLR_ACH0_IDX BIT(0)
654 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
656 #define R_AX_RXBD_RWPTR_CLR 0x1018
658 #define B_AX_CLR_RXQ_IDX BIT(0)
659 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
661 #define R_AX_TXBD_RWPTR_CLR2 0x1314
663 #define B_AX_CLR_CH10_IDX BIT(0)
664 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
666 #define R_AX_PCIE_DMA_BUSY1 0x101C
683 #define B_AX_RXQ_BUSY BIT(0)
692 #define R_AX_PCIE_DMA_BUSY2 0x131C
694 #define B_AX_CH10_BUSY BIT(0)
696 #define R_BE_HAXI_DMA_STOP1 0xB010
712 #define B_BE_STOP_CH0 BIT(0)
721 #define R_BE_CH0_TXBD_NUM_V1 0xB030
722 #define R_BE_CH1_TXBD_NUM_V1 0xB032
723 #define R_BE_CH2_TXBD_NUM_V1 0xB034
724 #define R_BE_CH3_TXBD_NUM_V1 0xB036
725 #define R_BE_CH4_TXBD_NUM_V1 0xB038
726 #define R_BE_CH5_TXBD_NUM_V1 0xB03A
727 #define R_BE_CH6_TXBD_NUM_V1 0xB03C
728 #define R_BE_CH7_TXBD_NUM_V1 0xB03E
729 #define R_BE_CH8_TXBD_NUM_V1 0xB040
730 #define R_BE_CH9_TXBD_NUM_V1 0xB042
731 #define R_BE_CH10_TXBD_NUM_V1 0xB044
732 #define R_BE_CH11_TXBD_NUM_V1 0xB046
733 #define R_BE_CH12_TXBD_NUM_V1 0xB048
734 #define R_BE_CH13_TXBD_NUM_V1 0xB04C
735 #define R_BE_CH14_TXBD_NUM_V1 0xB04E
737 #define R_BE_RXQ0_RXBD_NUM_V1 0xB050
738 #define R_BE_RPQ0_RXBD_NUM_V1 0xB052
740 #define R_BE_CH0_TXBD_IDX_V1 0xB100
741 #define R_BE_CH1_TXBD_IDX_V1 0xB104
742 #define R_BE_CH2_TXBD_IDX_V1 0xB108
743 #define R_BE_CH3_TXBD_IDX_V1 0xB10C
744 #define R_BE_CH4_TXBD_IDX_V1 0xB110
745 #define R_BE_CH5_TXBD_IDX_V1 0xB114
746 #define R_BE_CH6_TXBD_IDX_V1 0xB118
747 #define R_BE_CH7_TXBD_IDX_V1 0xB11C
748 #define R_BE_CH8_TXBD_IDX_V1 0xB120
749 #define R_BE_CH9_TXBD_IDX_V1 0xB124
750 #define R_BE_CH10_TXBD_IDX_V1 0xB128
751 #define R_BE_CH11_TXBD_IDX_V1 0xB12C
752 #define R_BE_CH12_TXBD_IDX_V1 0xB130
753 #define R_BE_CH13_TXBD_IDX_V1 0xB134
754 #define R_BE_CH14_TXBD_IDX_V1 0xB138
756 #define R_BE_RXQ0_RXBD_IDX_V1 0xB160
757 #define R_BE_RPQ0_RXBD_IDX_V1 0xB164
759 #define R_BE_CH0_TXBD_DESA_L_V1 0xB200
760 #define R_BE_CH0_TXBD_DESA_H_V1 0xB204
761 #define R_BE_CH1_TXBD_DESA_L_V1 0xB208
762 #define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
763 #define R_BE_CH2_TXBD_DESA_L_V1 0xB210
764 #define R_BE_CH2_TXBD_DESA_H_V1 0xB214
765 #define R_BE_CH3_TXBD_DESA_L_V1 0xB218
766 #define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
767 #define R_BE_CH4_TXBD_DESA_L_V1 0xB220
768 #define R_BE_CH4_TXBD_DESA_H_V1 0xB224
769 #define R_BE_CH5_TXBD_DESA_L_V1 0xB228
770 #define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
771 #define R_BE_CH6_TXBD_DESA_L_V1 0xB230
772 #define R_BE_CH6_TXBD_DESA_H_V1 0xB234
773 #define R_BE_CH7_TXBD_DESA_L_V1 0xB238
774 #define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
775 #define R_BE_CH8_TXBD_DESA_L_V1 0xB240
776 #define R_BE_CH8_TXBD_DESA_H_V1 0xB244
777 #define R_BE_CH9_TXBD_DESA_L_V1 0xB248
778 #define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
779 #define R_BE_CH10_TXBD_DESA_L_V1 0xB250
780 #define R_BE_CH10_TXBD_DESA_H_V1 0xB254
781 #define R_BE_CH11_TXBD_DESA_L_V1 0xB258
782 #define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
783 #define R_BE_CH12_TXBD_DESA_L_V1 0xB260
784 #define R_BE_CH12_TXBD_DESA_H_V1 0xB264
785 #define R_BE_CH13_TXBD_DESA_L_V1 0xB268
786 #define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
787 #define R_BE_CH14_TXBD_DESA_L_V1 0xB270
788 #define R_BE_CH14_TXBD_DESA_H_V1 0xB274
790 #define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
791 #define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
792 #define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
793 #define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
796 #define R_AX_PCIE_INIT_CFG2 0x1004
799 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
801 #define R_AX_PCIE_PS_CTRL 0x1008
804 #define R_AX_INT_MIT_RX 0x10D4
808 #define AX_RXTIMER_UNIT_64US 0
813 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
815 #define R_AX_DBG_ERR_FLAG_V1 0x1104
817 #define R_AX_INT_MIT_RX_V1 0x1184
822 #define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
824 #define R_AX_DBG_ERR_FLAG 0x11C4
833 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
835 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
837 #define B_AX_CLR_CH10_IDX BIT(0)
839 #define R_AX_LBC_WATCHDOG 0x11D8
842 #define B_AX_LBC_EN BIT(0)
844 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200
846 #define B_AX_CLR_RXQ_IDX BIT(0)
848 #define R_AX_HAXI_EXP_CTRL 0x1204
849 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
851 #define R_AX_PCIE_EXP_CTRL 0x13F0
856 #define R_AX_PCIE_RX_PREF_ADV 0x13F4
857 #define B_AX_RXDMA_PREF_ADV_EN BIT(0)
859 #define R_AX_PCIE_HRPWM_V1 0x30C0
860 #define R_AX_PCIE_CRPWM 0x30C4
862 #define R_AX_LBC_WATCHDOG_V1 0x30D8
864 #define R_BE_PCIE_HRPWM 0x30C0
865 #define R_BE_PCIE_CRPWM 0x30C4
867 #define R_BE_L1_2_CTRL_HCILDO 0x3110
868 #define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
870 #define R_BE_PL1_DBG_INFO 0x3120
872 #define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
874 #define R_BE_PCIE_MIT0_TMR 0x3330
876 #define BE_MIT0_TMR_UNIT_1MS 0
880 #define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
882 #define R_BE_PCIE_MIT0_CNT 0x3334
886 #define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
888 #define R_BE_PCIE_MIT_CH_EN 0x3338
911 #define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
913 #define R_BE_SER_PL1_CTRL 0x34A8
917 #define B_BE_PL1_TIMER_CLEAR BIT(0)
919 #define R_BE_REG_PL1_MASK 0x34B0
925 #define B_BE_SER_PMU_IMR BIT(0)
927 #define R_BE_RX_APPEND_MODE 0x8920
929 #define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
931 #define R_BE_TXBD_RWPTR_CLR1 0xB014
946 #define B_BE_CLR_CH0_IDX BIT(0)
948 #define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
954 #define B_BE_CLR_RXQ0_IDX BIT(0)
956 #define R_BE_HAXI_DMA_BUSY1 0xB01C
981 #define B_BE_CH0_BUSY BIT(0)
988 #define R_BE_HAXI_EXP_CTRL_V1 0xB020
992 #define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1005 #define RTW89_PCIE_CAPABILITY_SPEED 0x7C
1006 #define RTW89_PCIE_SUPPORT_GEN_MASK GENMASK(3, 0)
1007 #define RTW89_PCIE_L1_STS_V1 0x80
1009 #define RTW89_PCIE_GEN1_SPEED 0x01
1010 #define RTW89_PCIE_GEN2_SPEED 0x02
1011 #define RTW89_PCIE_PHY_RATE 0x82
1012 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
1013 #define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
1014 #define RTW89_PCIE_L1SS_STS_V1 0x0168
1018 #define RTW89_PCIE_BIT_PCI_L12 BIT(0)
1019 #define RTW89_PCIE_ASPM_CTRL 0x070F
1021 #define RTW89_L0DLY_MASK GENMASK(2, 0)
1022 #define RTW89_PCIE_TIMER_CTRL 0x0718
1024 #define RTW89_PCIE_L1_CTRL 0x0719
1027 #define RTW89_PCIE_CLK_CTRL 0x0725
1028 #define RTW89_PCIE_FTS 0x080C
1030 #define RTW89_PCIE_RST_MSTATE 0x0B48
1031 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
1039 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1043 PCIE_L0SDLY_1US = 0,
1060 PCIE_CLKDLY_HW_0 = 0,
1061 PCIE_CLKDLY_HW_30US = 0x1,
1062 PCIE_CLKDLY_HW_50US = 0x2,
1063 PCIE_CLKDLY_HW_100US = 0x3,
1064 PCIE_CLKDLY_HW_150US = 0x4,
1065 PCIE_CLKDLY_HW_200US = 0x5,
1071 MAC_AX_BD_DEF = 0xFE
1077 MAC_AX_RXBD_DEF = 0xFE
1083 MAC_AX_TAG_DEF = 0xFE
1087 MAC_AX_TX_BURST_16B = 0,
1090 MAC_AX_TX_BURST_V1_64B = 0,
1098 MAC_AX_TX_BURST_DEF = 0xFE
1102 MAC_AX_RX_BURST_16B = 0,
1105 MAC_AX_RX_BURST_V1_64B = 0,
1108 MAC_AX_RX_BURST_V1_256B = 0,
1109 MAC_AX_RX_BURST_DEF = 0xFE
1123 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1135 MAC_AX_TAG_NUM_DEF = 0xFE
1139 MAC_AX_LBC_TMR_8US = 0,
1150 MAC_AX_LBC_TMR_DEF = 0xFE
1154 MAC_AX_PCIE_DISABLE = 0,
1156 MAC_AX_PCIE_DEFAULT = 0xFE,
1157 MAC_AX_PCIE_IGNORE = 0xFF
1164 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1302 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
1314 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
1325 #define RTW89_TX_DONE 0x0
1326 #define RTW89_TX_RETRY_LIMIT 0x1
1327 #define RTW89_TX_LIFE_TIME 0x2
1328 #define RTW89_TX_MACID_DROP 0x3
1330 #define RTW89_PCI_RPP_MACID GENMASK(7, 0)
1344 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
1385 #define RTW89_RX_TAG_MAX 0x1fff
1393 u16 tag; /* range from 0x0001 ~ 0x1fff */
1501 txwd->len = 0; in rtw89_pci_dequeue_txwd()
1513 memset(txwd->vaddr, 0, wd_ring->page_size); in rtw89_pci_enqueue_txwd()
1520 return val == 0xffffffff || val == 0xeaeaeaea; in rtw89_pci_ltr_is_err_reg_val()
1650 return 0; in rtw89_pci_ops_mac_pre_deinit()