Lines Matching defs:rtl_phy

1306 struct rtl_phy {  struct
1307 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
1308 	struct init_gain initgain_backup;
1309 	enum io_type current_io_type;
1311 	u8 rf_mode;
1312 	u8 rf_type;
1313 	u8 current_chan_bw;
1314 	u8 set_bwmode_inprogress;
1315 	u8 sw_chnl_inprogress;
1316 	u8 sw_chnl_stage;
1317 	u8 sw_chnl_step;
1318 	u8 current_channel;
1319 	u8 set_io_inprogress;
1320 	u8 lck_inprogress;
1323 	s32 reg_e94;
1324 	s32 reg_e9c;
1325 	s32 reg_ea4;
1326 	s32 reg_eac;
1327 	s32 reg_eb4;
1328 	s32 reg_ebc;
1329 	s32 reg_ec4;
1330 	s32 reg_ecc;
1331 	u32 reg_c04, reg_c08, reg_874;
1332 	u32 adda_backup[16];
1333 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1334 	u32 iqk_bb_backup[10];
1335 	bool iqk_initialized;
1337 	bool rfpath_rx_enable[MAX_RF_PATH];
1338 	u8 reg_837;
1340 	bool need_iqk;
1341 	struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1343 	bool rfpi_enable;
1345 	u8 pwrgroup_cnt;
1346 	u8 cck_high_power;
1348 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1350 	u32 mcs_offset[MAX_PG_GROUP][16];
1351 	u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1355 	u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1358 	u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1361 	u8 default_initialgain[4];
1364 	u8 cur_cck_txpwridx;
1365 	u8 cur_ofdm24g_txpwridx;
1366 	u8 cur_bw20_txpwridx;
1367 	u8 cur_bw40_txpwridx;
1369 	s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1374 	s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1380 	u32 rfreg_chnlval[2];
1381 	u32 reg_rf3c[2];	/* pathA / pathB  */
1383 	u32 backup_rf_0x1a;/*92ee*/
1385 	u8 framesync;
1386 	u32 framesync_c34;
1388 	u8 num_total_rfpath;
1389 	struct phy_parameters hwparam_tables[MAX_TAB];
1390 	u16 rf_pathmap;
1392 	enum rt_polarity_ctl polarity_ctl;