Lines Matching +full:cmd +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
10 #include <linux/crc-itu-t.h>
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
52 } gpios; member
163 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_parse_gpios()
164 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_parse_gpios()
165 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_parse_gpios() local
168 gpios->enable = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
171 if (gpios->enable) { in wilc_parse_gpios()
173 gpios->reset = devm_gpiod_get(&spi->dev, in wilc_parse_gpios()
175 if (IS_ERR(gpios->reset)) { in wilc_parse_gpios()
176 dev_err(&spi->dev, "missing reset gpio.\n"); in wilc_parse_gpios()
177 return PTR_ERR(gpios->reset); in wilc_parse_gpios()
180 gpios->reset = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
188 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_wlan_power()
189 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_wlan_power() local
193 gpiod_set_value(gpios->enable, 1); in wilc_wlan_power()
196 gpiod_set_value(gpios->reset, 1); in wilc_wlan_power()
199 gpiod_set_value(gpios->reset, 0); in wilc_wlan_power()
201 gpiod_set_value(gpios->enable, 0); in wilc_wlan_power()
213 return -ENOMEM; in wilc_bus_probe()
215 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); in wilc_bus_probe()
220 wilc->dev = &spi->dev; in wilc_bus_probe()
221 wilc->bus_data = spi_priv; in wilc_bus_probe()
222 wilc->dev_irq_num = spi->irq; in wilc_bus_probe()
228 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); in wilc_bus_probe()
229 if (IS_ERR(wilc->rtc_clk)) { in wilc_bus_probe()
230 ret = PTR_ERR(wilc->rtc_clk); in wilc_bus_probe()
233 clk_prepare_enable(wilc->rtc_clk); in wilc_bus_probe()
247 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_bus_remove()
249 clk_disable_unprepare(wilc->rtc_clk); in wilc_bus_remove()
281 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx()
297 return -ENOMEM; in wilc_spi_tx()
300 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); in wilc_spi_tx()
309 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx()
313 dev_err(&spi->dev, in wilc_spi_tx()
316 ret = -EINVAL; in wilc_spi_tx()
324 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_rx()
341 return -ENOMEM; in wilc_spi_rx()
352 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_rx()
355 dev_err(&spi->dev, in wilc_spi_rx()
358 ret = -EINVAL; in wilc_spi_rx()
366 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx_rx()
390 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx_rx()
392 dev_err(&spi->dev, in wilc_spi_tx_rx()
395 ret = -EINVAL; in wilc_spi_tx_rx()
403 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_write()
404 struct wilc_spi *spi_priv = wilc->bus_data; in spi_data_write()
407 u8 cmd, order, crc[2]; in spi_data_write() local
429 cmd = 0xf0; in spi_data_write()
430 cmd |= order; in spi_data_write()
432 if (wilc_spi_tx(wilc, &cmd, 1)) { in spi_data_write()
433 dev_err(&spi->dev, in spi_data_write()
434 "Failed data block cmd write, bus error...\n"); in spi_data_write()
435 result = -EINVAL; in spi_data_write()
443 dev_err(&spi->dev, in spi_data_write()
445 result = -EINVAL; in spi_data_write()
452 if (spi_priv->crc16_enabled) { in spi_data_write()
457 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); in spi_data_write()
458 result = -EINVAL; in spi_data_write()
467 sz -= nbytes; in spi_data_write()
483 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, in wilc_spi_single_read() argument
486 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_single_read()
487 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_single_read()
498 c->cmd_type = cmd; in wilc_spi_single_read()
499 if (cmd == CMD_SINGLE_READ) { in wilc_spi_single_read()
500 c->u.simple_cmd.addr[0] = adr >> 16; in wilc_spi_single_read()
501 c->u.simple_cmd.addr[1] = adr >> 8; in wilc_spi_single_read()
502 c->u.simple_cmd.addr[2] = adr; in wilc_spi_single_read()
503 } else if (cmd == CMD_INTERNAL_READ) { in wilc_spi_single_read()
504 c->u.simple_cmd.addr[0] = adr >> 8; in wilc_spi_single_read()
506 c->u.simple_cmd.addr[0] |= BIT(7); in wilc_spi_single_read()
507 c->u.simple_cmd.addr[1] = adr; in wilc_spi_single_read()
508 c->u.simple_cmd.addr[2] = 0x0; in wilc_spi_single_read()
510 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); in wilc_spi_single_read()
511 return -EINVAL; in wilc_spi_single_read()
517 if (spi_priv->crc7_enabled) { in wilc_spi_single_read()
518 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_single_read()
524 dev_err(&spi->dev, in wilc_spi_single_read()
527 return -EINVAL; in wilc_spi_single_read()
531 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_single_read()
532 return -EINVAL; in wilc_spi_single_read()
536 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_single_read()
537 if (!spi_priv->probing_crc) in wilc_spi_single_read()
538 dev_err(&spi->dev, in wilc_spi_single_read()
539 "Failed cmd, cmd (%02x), resp (%02x)\n", in wilc_spi_single_read()
540 cmd, r->rsp_cmd_type); in wilc_spi_single_read()
541 return -EINVAL; in wilc_spi_single_read()
544 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_single_read()
545 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_single_read()
546 r->status); in wilc_spi_single_read()
547 return -EINVAL; in wilc_spi_single_read()
551 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) in wilc_spi_single_read()
555 dev_err(&spi->dev, "Error, data start missing\n"); in wilc_spi_single_read()
556 return -EINVAL; in wilc_spi_single_read()
559 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; in wilc_spi_single_read()
562 memcpy(b, r_data->data, 4); in wilc_spi_single_read()
564 if (!clockless && spi_priv->crc16_enabled) { in wilc_spi_single_read()
565 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; in wilc_spi_single_read()
566 crc_calc = crc_itu_t(0xffff, r_data->data, 4); in wilc_spi_single_read()
568 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_single_read()
571 return -EINVAL; in wilc_spi_single_read()
578 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, in wilc_spi_write_cmd() argument
581 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_cmd()
582 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_write_cmd()
591 c->cmd_type = cmd; in wilc_spi_write_cmd()
592 if (cmd == CMD_INTERNAL_WRITE) { in wilc_spi_write_cmd()
593 c->u.internal_w_cmd.addr[0] = adr >> 8; in wilc_spi_write_cmd()
595 c->u.internal_w_cmd.addr[0] |= BIT(7); in wilc_spi_write_cmd()
597 c->u.internal_w_cmd.addr[1] = adr; in wilc_spi_write_cmd()
598 c->u.internal_w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
600 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
601 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
602 } else if (cmd == CMD_SINGLE_WRITE) { in wilc_spi_write_cmd()
603 c->u.w_cmd.addr[0] = adr >> 16; in wilc_spi_write_cmd()
604 c->u.w_cmd.addr[1] = adr >> 8; in wilc_spi_write_cmd()
605 c->u.w_cmd.addr[2] = adr; in wilc_spi_write_cmd()
606 c->u.w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
608 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
609 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
611 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); in wilc_spi_write_cmd()
612 return -EINVAL; in wilc_spi_write_cmd()
615 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
621 dev_err(&spi->dev, in wilc_spi_write_cmd()
624 return -EINVAL; in wilc_spi_write_cmd()
628 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_write_cmd()
629 return -EINVAL; in wilc_spi_write_cmd()
637 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_write_cmd()
638 dev_err(&spi->dev, in wilc_spi_write_cmd()
639 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_write_cmd()
640 cmd, r->rsp_cmd_type); in wilc_spi_write_cmd()
641 return -EINVAL; in wilc_spi_write_cmd()
644 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_write_cmd()
645 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_write_cmd()
646 r->status); in wilc_spi_write_cmd()
647 return -EINVAL; in wilc_spi_write_cmd()
653 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) in wilc_spi_dma_rw() argument
655 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_dma_rw()
656 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_dma_rw()
668 c->cmd_type = cmd; in wilc_spi_dma_rw()
669 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { in wilc_spi_dma_rw()
670 c->u.dma_cmd.addr[0] = adr >> 16; in wilc_spi_dma_rw()
671 c->u.dma_cmd.addr[1] = adr >> 8; in wilc_spi_dma_rw()
672 c->u.dma_cmd.addr[2] = adr; in wilc_spi_dma_rw()
673 c->u.dma_cmd.size[0] = sz >> 8; in wilc_spi_dma_rw()
674 c->u.dma_cmd.size[1] = sz; in wilc_spi_dma_rw()
676 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
677 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
678 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { in wilc_spi_dma_rw()
679 c->u.dma_cmd_ext.addr[0] = adr >> 16; in wilc_spi_dma_rw()
680 c->u.dma_cmd_ext.addr[1] = adr >> 8; in wilc_spi_dma_rw()
681 c->u.dma_cmd_ext.addr[2] = adr; in wilc_spi_dma_rw()
682 c->u.dma_cmd_ext.size[0] = sz >> 16; in wilc_spi_dma_rw()
683 c->u.dma_cmd_ext.size[1] = sz >> 8; in wilc_spi_dma_rw()
684 c->u.dma_cmd_ext.size[2] = sz; in wilc_spi_dma_rw()
686 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
687 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
689 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", in wilc_spi_dma_rw()
690 cmd); in wilc_spi_dma_rw()
691 return -EINVAL; in wilc_spi_dma_rw()
693 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
699 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", in wilc_spi_dma_rw()
701 return -EINVAL; in wilc_spi_dma_rw()
705 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_dma_rw()
706 return -EINVAL; in wilc_spi_dma_rw()
710 if (r->rsp_cmd_type != cmd) { in wilc_spi_dma_rw()
711 dev_err(&spi->dev, in wilc_spi_dma_rw()
712 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_dma_rw()
713 cmd, r->rsp_cmd_type); in wilc_spi_dma_rw()
714 return -EINVAL; in wilc_spi_dma_rw()
717 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_dma_rw()
718 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_dma_rw()
719 r->status); in wilc_spi_dma_rw()
720 return -EINVAL; in wilc_spi_dma_rw()
723 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) in wilc_spi_dma_rw()
738 dev_err(&spi->dev, in wilc_spi_dma_rw()
740 return -EINVAL; in wilc_spi_dma_rw()
744 } while (retry--); in wilc_spi_dma_rw()
750 dev_err(&spi->dev, in wilc_spi_dma_rw()
752 return -EINVAL; in wilc_spi_dma_rw()
758 if (spi_priv->crc16_enabled) { in wilc_spi_dma_rw()
760 dev_err(&spi->dev, in wilc_spi_dma_rw()
762 return -EINVAL; in wilc_spi_dma_rw()
767 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_dma_rw()
770 return -EINVAL; in wilc_spi_dma_rw()
775 sz -= nbytes; in wilc_spi_dma_rw()
780 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) in wilc_spi_special_cmd() argument
782 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_special_cmd()
783 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_special_cmd()
789 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) in wilc_spi_special_cmd()
790 return -EINVAL; in wilc_spi_special_cmd()
795 c->cmd_type = cmd; in wilc_spi_special_cmd()
797 if (cmd == CMD_RESET) in wilc_spi_special_cmd()
798 memset(c->u.simple_cmd.addr, 0xFF, 3); in wilc_spi_special_cmd()
803 if (spi_priv->crc7_enabled) { in wilc_spi_special_cmd()
804 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_special_cmd()
808 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_special_cmd()
810 return -EINVAL; in wilc_spi_special_cmd()
814 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_special_cmd()
815 return -EINVAL; in wilc_spi_special_cmd()
819 if (r->rsp_cmd_type != cmd) { in wilc_spi_special_cmd()
820 if (!spi_priv->probing_crc) in wilc_spi_special_cmd()
821 dev_err(&spi->dev, in wilc_spi_special_cmd()
822 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_special_cmd()
823 cmd, r->rsp_cmd_type); in wilc_spi_special_cmd()
824 return -EINVAL; in wilc_spi_special_cmd()
827 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_special_cmd()
828 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_special_cmd()
829 r->status); in wilc_spi_special_cmd()
830 return -EINVAL; in wilc_spi_special_cmd()
837 struct spi_device *spi = to_spi_device(wl->dev); in wilc_spi_reset_cmd_sequence()
838 struct wilc_spi *spi_priv = wl->bus_data; in wilc_spi_reset_cmd_sequence()
840 if (!spi_priv->probing_crc) in wilc_spi_reset_cmd_sequence()
841 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); in wilc_spi_reset_cmd_sequence()
850 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read_reg()
852 u8 cmd = CMD_SINGLE_READ; in wilc_spi_read_reg() local
858 cmd = CMD_INTERNAL_READ; in wilc_spi_read_reg()
863 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); in wilc_spi_read_reg()
873 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); in wilc_spi_read_reg()
882 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read()
887 return -EINVAL; in wilc_spi_read()
895 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); in wilc_spi_read()
905 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_write()
914 dev_err(&spi->dev, "Failed internal write cmd...\n"); in spi_internal_write()
924 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_read()
925 struct wilc_spi *spi_priv = wilc->bus_data; in spi_internal_read()
936 if (!spi_priv->probing_crc) in spi_internal_read()
937 dev_err(&spi->dev, "Failed internal read cmd...\n"); in spi_internal_read()
953 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_reg()
955 u8 cmd = CMD_SINGLE_WRITE; in wilc_spi_write_reg() local
961 cmd = CMD_INTERNAL_WRITE; in wilc_spi_write_reg()
966 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); in wilc_spi_write_reg()
970 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); in wilc_spi_write_reg()
980 static int spi_data_rsp(struct wilc *wilc, u8 cmd) in spi_data_rsp() argument
982 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_rsp()
992 * second-to-last packet before the one for the final packet. in spi_data_rsp()
1000 dev_err(&spi->dev, "Failed bus error...\n"); in spi_data_rsp()
1004 for (i = sizeof(rsp) - 2; i >= 0; --i) in spi_data_rsp()
1009 dev_err(&spi->dev, in spi_data_rsp()
1012 return -1; in spi_data_rsp()
1019 dev_err(&spi->dev, "Data response error (%02x %02x)\n", in spi_data_rsp()
1021 return -1; in spi_data_rsp()
1028 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write()
1036 return -EINVAL; in wilc_spi_write()
1042 dev_err(&spi->dev, in wilc_spi_write()
1043 "Failed cmd, write block (%08x)...\n", addr); in wilc_spi_write()
1053 dev_err(&spi->dev, "Failed block data write...\n"); in wilc_spi_write()
1063 dev_err(&spi->dev, "Failed block data rsp...\n"); in wilc_spi_write()
1080 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_reset()
1081 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_reset()
1085 if (result && !spi_priv->probing_crc) in wilc_spi_reset()
1086 dev_err(&spi->dev, "Failed cmd reset\n"); in wilc_spi_reset()
1093 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_is_init()
1095 return spi_priv->isinit; in wilc_spi_is_init()
1100 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_deinit()
1102 spi_priv->isinit = false; in wilc_spi_deinit()
1109 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_init()
1110 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_init()
1115 if (spi_priv->isinit) { in wilc_spi_init()
1121 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1135 spi_priv->probing_crc = true; in wilc_spi_init()
1136 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1137 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ in wilc_spi_init()
1142 spi_priv->crc7_enabled = !enable_crc7; in wilc_spi_init()
1145 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); in wilc_spi_init()
1161 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); in wilc_spi_init()
1166 dev_err(&spi->dev, in wilc_spi_init()
1172 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1173 spi_priv->crc16_enabled = enable_crc16; in wilc_spi_init()
1175 /* re-read to make sure new settings are in effect: */ in wilc_spi_init()
1178 spi_priv->probing_crc = false; in wilc_spi_init()
1185 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1189 spi_priv->isinit = true; in wilc_spi_init()
1199 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); in wilc_spi_read_size()
1207 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, in wilc_spi_read_int()
1219 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1225 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1230 retry--; in wilc_spi_clear_int_ext()
1237 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_sync_ext()
1242 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); in wilc_spi_sync_ext()
1243 return -EINVAL; in wilc_spi_sync_ext()
1251 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1258 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1268 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1273 for (i = 0; (i < 5) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1278 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1285 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1290 for (i = 0; (i < 3) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1295 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()