Lines Matching +full:prefetch +full:- +full:dma
1 // SPDX-License-Identifier: ISC
8 #include "dma.h"
15 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_irq_handler()
17 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) in mt792x_irq_handler()
20 tasklet_schedule(&dev->mt76.irq_tasklet); in mt792x_irq_handler()
29 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_irq_tasklet()
32 mt76_wr(dev, irq_map->host_irq_enable, 0); in mt792x_irq_tasklet()
35 intr &= dev->mt76.mmio.irqmask; in mt792x_irq_tasklet()
38 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt792x_irq_tasklet()
40 mask |= intr & (irq_map->rx.data_complete_mask | in mt792x_irq_tasklet()
41 irq_map->rx.wm_complete_mask | in mt792x_irq_tasklet()
42 irq_map->rx.wm2_complete_mask); in mt792x_irq_tasklet()
43 if (intr & dev->irq_map->tx.mcu_complete_mask) in mt792x_irq_tasklet()
44 mask |= dev->irq_map->tx.mcu_complete_mask; in mt792x_irq_tasklet()
53 mask |= irq_map->rx.data_complete_mask; in mt792x_irq_tasklet()
54 intr |= irq_map->rx.data_complete_mask; in mt792x_irq_tasklet()
58 mt76_set_irq_mask(&dev->mt76, irq_map->host_irq_enable, mask, 0); in mt792x_irq_tasklet()
60 if (intr & dev->irq_map->tx.all_complete_mask) in mt792x_irq_tasklet()
61 napi_schedule(&dev->mt76.tx_napi); in mt792x_irq_tasklet()
63 if (intr & irq_map->rx.wm_complete_mask) in mt792x_irq_tasklet()
64 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); in mt792x_irq_tasklet()
66 if (intr & irq_map->rx.wm2_complete_mask) in mt792x_irq_tasklet()
67 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); in mt792x_irq_tasklet()
69 if (intr & irq_map->rx.data_complete_mask) in mt792x_irq_tasklet()
70 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); in mt792x_irq_tasklet()
77 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_rx_poll_complete()
80 mt76_connac_irq_enable(mdev, irq_map->rx.data_complete_mask); in mt792x_rx_poll_complete()
82 mt76_connac_irq_enable(mdev, irq_map->rx.wm2_complete_mask); in mt792x_rx_poll_complete()
84 mt76_connac_irq_enable(mdev, irq_map->rx.wm_complete_mask); in mt792x_rx_poll_complete()
88 #define PREFETCH(base, depth) ((base) << 16 | (depth)) macro
91 if (is_mt7925(&dev->mt76)) { in mt792x_dma_prefetch()
93 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4)); in mt792x_dma_prefetch()
94 mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4)); in mt792x_dma_prefetch()
95 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4)); in mt792x_dma_prefetch()
96 mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4)); in mt792x_dma_prefetch()
98 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10)); in mt792x_dma_prefetch()
99 mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10)); in mt792x_dma_prefetch()
100 mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10)); in mt792x_dma_prefetch()
101 mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10)); in mt792x_dma_prefetch()
102 mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4)); in mt792x_dma_prefetch()
103 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4)); in mt792x_dma_prefetch()
106 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); in mt792x_dma_prefetch()
107 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4)); in mt792x_dma_prefetch()
108 mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4)); in mt792x_dma_prefetch()
109 mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4)); in mt792x_dma_prefetch()
110 mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4)); in mt792x_dma_prefetch()
112 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4)); in mt792x_dma_prefetch()
113 mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4)); in mt792x_dma_prefetch()
114 mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4)); in mt792x_dma_prefetch()
115 mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4)); in mt792x_dma_prefetch()
116 mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4)); in mt792x_dma_prefetch()
117 mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4)); in mt792x_dma_prefetch()
118 mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4)); in mt792x_dma_prefetch()
119 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4)); in mt792x_dma_prefetch()
120 mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4)); in mt792x_dma_prefetch()
126 if (is_mt7925(&dev->mt76)) in mt792x_dma_enable()
132 /* reset dma idx */ in mt792x_dma_enable()
152 mt76_connac_irq_enable(&dev->mt76, in mt792x_dma_enable()
153 dev->irq_map->tx.all_complete_mask | in mt792x_dma_enable()
154 dev->irq_map->rx.data_complete_mask | in mt792x_dma_enable()
155 dev->irq_map->rx.wm2_complete_mask | in mt792x_dma_enable()
156 dev->irq_map->rx.wm_complete_mask | in mt792x_dma_enable()
175 mt76_queue_reset(dev, dev->mphy.q_tx[i]); in mt792x_dma_reset()
178 mt76_queue_reset(dev, dev->mt76.q_mcu[i]); in mt792x_dma_reset()
180 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_dma_reset()
181 mt76_queue_reset(dev, &dev->mt76.q_rx[i]); in mt792x_dma_reset()
183 mt76_tx_status_check(&dev->mt76, true); in mt792x_dma_reset()
193 for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++) in mt792x_wpdma_reset()
194 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt792x_wpdma_reset()
196 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++) in mt792x_wpdma_reset()
197 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); in mt792x_wpdma_reset()
199 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_wpdma_reset()
200 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); in mt792x_wpdma_reset()
211 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_wpdma_reset()
220 struct mt76_connac_pm *pm = &dev->pm; in mt792x_wpdma_reinit_cond()
226 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_wpdma_reinit_cond()
231 dev_err(dev->mt76.dev, "wpdma reset failed\n"); in mt792x_wpdma_reinit_cond()
237 pm->stats.lp_wake++; in mt792x_wpdma_reinit_cond()
257 return -ETIMEDOUT; in mt792x_dma_disable()
303 mt76_dma_cleanup(&dev->mt76); in mt792x_dma_cleanup()
313 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt792x_poll_tx()
315 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt792x_poll_tx()
319 mt76_connac_tx_cleanup(&dev->mt76); in mt792x_poll_tx()
321 mt76_connac_irq_enable(&dev->mt76, in mt792x_poll_tx()
322 dev->irq_map->tx.all_complete_mask); in mt792x_poll_tx()
323 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt792x_poll_tx()
334 dev = container_of(napi->dev, struct mt792x_dev, mt76.napi_dev); in mt792x_poll_rx()
336 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt792x_poll_rx()
338 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt792x_poll_rx()
342 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt792x_poll_rx()
350 u32 addr = is_mt7921(&dev->mt76) ? 0x18000140 : 0x7c000140; in mt792x_wfsys_reset()
356 if (!__mt76_poll_msec(&dev->mt76, addr, WFSYS_SW_INIT_DONE, in mt792x_wfsys_reset()
358 return -ETIMEDOUT; in mt792x_wfsys_reset()