43 		.check_crc = 0,  in mt76_connac_mcu_start_patch()
51 #define MCU_PATCH_ADDRESS	0x200000
68 	    (is_mt7921(dev) && addr == 0x900000) ||  in mt76_connac_mcu_init_download()
69 	    (is_mt7925(dev) && addr == 0x900000) ||  in mt76_connac_mcu_init_download()
70 	    (is_mt7996(dev) && addr == 0x900000) ||  in mt76_connac_mcu_init_download()
71 	    (is_mt7992(dev) && addr == 0x900000))  in mt76_connac_mcu_init_download()
82 	int len, i, n_max_channels, n_2ch = 0, n_5ch = 0, n_6ch = 0;  in mt76_connac_mcu_set_channel_domain()
85 		u8 bw_2g; /* BW_20_40M		0  in mt76_connac_mcu_set_channel_domain()
99 		.bw_2g = 0,  in mt76_connac_mcu_set_channel_domain()
123 	for (i = 0; i < phy->sband_2g.sband.n_channels; i++) {  in mt76_connac_mcu_set_channel_domain()
130 		channel.pad = 0;  in mt76_connac_mcu_set_channel_domain()
135 	for (i = 0; i < phy->sband_5g.sband.n_channels; i++) {  in mt76_connac_mcu_set_channel_domain()
142 		channel.pad = 0;  in mt76_connac_mcu_set_channel_domain()
147 	for (i = 0; i < phy->sband_6g.sband.n_channels; i++) {  in mt76_connac_mcu_set_channel_domain()
154 		channel.pad = 0;  in mt76_connac_mcu_set_channel_domain()
195 		u8 ps_state; /* 0: device awake  in mt76_connac_mcu_set_vif_ps()
201 		.ps_state = vif->cfg.ps ? 2 : 0,  in mt76_connac_mcu_set_vif_ps()
224 		.pkt_thresh = cpu_to_le32(0x2),  in mt76_connac_mcu_set_rts_thresh()
281 		.muar_idx = wcid ? mvif->omac_idx : 0,  in __mt76_connac_mcu_alloc_sta_req()
333 	u32 type = 0;  in mt76_connac_mcu_bss_omac_tlv()
453 		uapsd->dac_map |= BIT(0);  in mt76_connac_mcu_sta_uapsd()
454 		uapsd->tac_map |= BIT(0);  in mt76_connac_mcu_sta_uapsd()
569 		generic->muar_idx = 0xe;  in mt76_connac_mcu_wtbl_generic_tlv()
624 	u32 cap = 0;  in mt76_connac_mcu_sta_he_tlv()
630 	if (elem->mac_cap_info[0] & IEEE80211_HE_MAC_CAP0_HTC_HE)  in mt76_connac_mcu_sta_he_tlv()
645 	if (elem->phy_cap_info[0] &  in mt76_connac_mcu_sta_he_tlv()
710 		if (elem->phy_cap_info[0] &  in mt76_connac_mcu_sta_he_tlv()
730 		HE_PHY(CAP0_CHANNEL_WIDTH_SET_MASK, elem->phy_cap_info[0]);  in mt76_connac_mcu_sta_he_tlv()
766 		if (elem->phy_cap_info[0] &  in mt76_connac_mcu_sta_he_tlv_v2()
792 	u8 mode = 0;  in mt76_connac_get_phy_mode_v2()
918 			     FIELD_PREP(RA_LEGACY_CCK, supp_rates & 0xf);  in mt76_connac_mcu_sta_tlv()
961 	u32 flags = 0;  in mt76_connac_mcu_wtbl_ht_tlv()
1095 		ba->sn = enable ? cpu_to_le16(params->ssn) : 0;  in mt76_connac_mcu_wtbl_ba_tlv()
1096 		ba->ba_winsize = enable ? cpu_to_le16(params->buf_size) : 0;  in mt76_connac_mcu_wtbl_ba_tlv()
1107 		ba->ba_winsize = enable ? cpu_to_le16(params->buf_size) : 0;  in mt76_connac_mcu_wtbl_ba_tlv()
1115 		for (i = 7; i > 0; i--) {  in mt76_connac_mcu_wtbl_ba_tlv()
1207 	if (err < 0)  in mt76_connac_mcu_uni_add_dev()
1240 		return 0;  in mt76_connac_mcu_sta_wed_update()
1243 		return 0;  in mt76_connac_mcu_sta_wed_update()
1304 	u8 mode = 0;  in mt76_connac_get_phy_mode()
1307 		return 0x38;  in mt76_connac_get_phy_mode()
1355 	u8 mode = 0;  in mt76_connac_get_phy_mode_ext()
1504 		rlm_req.rlm.ht_op_info = 0;  in mt76_connac_mcu_uni_set_chctx()
1600 	if (err < 0)  in mt76_connac_mcu_uni_add_bss()
1622 				.enable = 0,  in mt76_connac_mcu_uni_add_bss()
1623 				.bss_color = 0,  in mt76_connac_mcu_uni_add_bss()
1638 		if (err < 0)  in mt76_connac_mcu_uni_add_bss()
1652 	int n_ssids = 0, err, i, duration;  in mt76_connac_mcu_hw_scan()
1653 	int ext_channels_num = max_t(int, sreq->n_channels - 32, 0);  in mt76_connac_mcu_hw_scan()
1668 	mvif->scan_seq_num = (mvif->scan_seq_num + 1) & 0x7f;  in mt76_connac_mcu_hw_scan()
1674 	req->scan_type = sreq->n_ssids ? 1 : 0;  in mt76_connac_mcu_hw_scan()
1675 	req->probe_req_num = sreq->n_ssids ? 2 : 0;  in mt76_connac_mcu_hw_scan()
1678 	for (i = 0; i < sreq->n_ssids; i++) {  in mt76_connac_mcu_hw_scan()
1687 	req->ssid_type = n_ssids ? BIT(2) : BIT(0);  in mt76_connac_mcu_hw_scan()
1688 	req->ssid_type_ext = n_ssids ? BIT(0) : 0;  in mt76_connac_mcu_hw_scan()
1691 	duration = is_mt7921(phy->dev) ? 0 : MT76_CONNAC_SCAN_CHANNEL_TIME;  in mt76_connac_mcu_hw_scan()
1699 	if (sreq->n_channels == 0 || sreq->n_channels > 64) {  in mt76_connac_mcu_hw_scan()
1700 		req->channel_type = 0;  in mt76_connac_mcu_hw_scan()
1701 		req->channels_num = 0;  in mt76_connac_mcu_hw_scan()
1702 		req->ext_channels_num = 0;  in mt76_connac_mcu_hw_scan()
1709 	for (i = 0; i < req->channels_num + req->ext_channels_num; i++) {  in mt76_connac_mcu_hw_scan()
1729 	if (sreq->ie_len > 0) {  in mt76_connac_mcu_hw_scan()
1746 	if (err < 0)  in mt76_connac_mcu_hw_scan()
1796 	mvif->scan_seq_num = (mvif->scan_seq_num + 1) & 0x7f;  in mt76_connac_mcu_sched_scan_req()
1816 	for (i = 0; i < req->ssids_num; i++) {  in mt76_connac_mcu_sched_scan_req()
1823 	for (i = 0; i < req->match_num; i++) {  in mt76_connac_mcu_sched_scan_req()
1831 	req->channel_type = sreq->n_channels ? 4 : 0;  in mt76_connac_mcu_sched_scan_req()
1833 	for (i = 0; i < req->channels_num; i++) {  in mt76_connac_mcu_sched_scan_req()
1851 	for (i = 0; i < req->intervals_num; i++)  in mt76_connac_mcu_sched_scan_req()
1854 	if (sreq->ie_len > 0) {  in mt76_connac_mcu_sched_scan_req()
1869 		u8 active; /* 0: enabled 1: disabled */  in mt76_connac_mcu_sched_scan_enable()
1888 		.resp_type = 0,  in mt76_connac_mcu_chip_config()
1901 		.resp_type = 0,  in mt76_connac_mcu_set_deep_sleep()
1927 	return 0;  in mt76_connac_sta_state_dp()
1965 	for (i = 0; i < 2; i++) {  in mt76_connac_mcu_build_sku()
1969 	sku[offset++] = limits->mcs[0][0];  in mt76_connac_mcu_build_sku()
1972 	for (i = 0; i < ARRAY_SIZE(limits->mcs); i++) {  in mt76_connac_mcu_build_sku()
1982 	for (i = 0; i < ARRAY_SIZE(limits->ru); i++) {  in mt76_connac_mcu_build_sku()
2010 	for (i = 0; i < sband->n_channels; i++) {  in mt76_connac_get_ch_power()
2066 	int i, n_chan, batch_size, idx = 0, tx_power, last_ch, err = 0;  in mt76_connac_mcu_rate_txpower_band()
2099 	for (i = 0; i < batch_size; i++) {  in mt76_connac_mcu_rate_txpower_band()
2130 		for (j = 0; j < num_ch; j++, idx++) {  in mt76_connac_mcu_rate_txpower_band()
2157 		if (err < 0)  in mt76_connac_mcu_rate_txpower_band()
2173 		if (err < 0)  in mt76_connac_mcu_set_rate_txpower()
2179 		if (err < 0)  in mt76_connac_mcu_set_rate_txpower()
2185 		if (err < 0)  in mt76_connac_mcu_set_rate_txpower()
2189 	return 0;  in mt76_connac_mcu_set_rate_txpower()
2227 	for (i = 0; i < len; i++)  in mt76_connac_mcu_update_arp_filter()
2484 			.gpio_pin = 0xff, /* follow fw about GPIO pin */  in mt76_connac_mcu_set_wow_ctrl()
2517 			u8 hif_type; /* 0x0: HIF_SDIO  in mt76_connac_mcu_set_hif_suspend()
2518 				      * 0x1: HIF_USB  in mt76_connac_mcu_set_hif_suspend()
2519 				      * 0x2: HIF_PCIE  in mt76_connac_mcu_set_hif_suspend()
2530 			.tag = cpu_to_le16(0), /* 0: UNI_HIF_CTRL_BASIC */  in mt76_connac_mcu_set_hif_suspend()
2541 		req.hdr.hif_type = 0;  in mt76_connac_mcu_set_hif_suspend()
2562 	for (i = 0; i < wowlan->n_patterns; i++)  in mt76_connac_mcu_set_suspend_iter()
2621 		sec_key = &sec->key[0];  in mt76_connac_mcu_sta_key_tlv()
2659 		sec->n_cipher = 0;  in mt76_connac_mcu_sta_key_tlv()
2663 	return 0;  in mt76_connac_mcu_sta_key_tlv()
2700 	if (ext_bss_idx < 0)  in mt76_connac_mcu_bss_ext_tlv()
2784 	return 0;  in mt76_connac_mcu_bss_basic_tlv()
2860 	int i, offset = 0, max_len = mt76_is_sdio(dev) ? 2048 : 4096;  in mt76_connac_mcu_send_ram_firmware()
2861 	u32 override = 0, option = 0;  in mt76_connac_mcu_send_ram_firmware()
2863 	for (i = 0; i < hdr->n_region; i++) {  in mt76_connac_mcu_send_ram_firmware()
2940 		return 0;  in mt76_connac2_load_ram()
3010 		return 0;  in mt76_connac2_load_patch()
3029 	dev_info(dev->dev, "HW/SW Version: 0x%x, Build Time: %.16s\n",  in mt76_connac2_load_patch()
3032 	for (i = 0; i < be32_to_cpu(hdr->desc.n_region); i++) {  in mt76_connac2_load_patch()
3099 	seq = ++dev->mcu.msg_seq & 0xf;  in mt76_connac2_mcu_fill_message()
3101 		seq = ++dev->mcu.msg_seq & 0xf;  in mt76_connac2_mcu_fill_message()
3112 	txd[0] = cpu_to_le32(val);  in mt76_connac2_mcu_fill_message()
3158 	return 0;  in mt76_connac2_mcu_fill_message()