Lines Matching +full:25 +full:- +full:18

1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH			BIT(18)
42 #define MT_RXD1_NORMAL_GROUP_3		BIT(18)
48 #define MT_RXD1_NORMAL_ICV_ERR		BIT(25)
65 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
78 #define MT_RXD3_NORMAL_HTC_VLD		BIT(18)
101 /* P-RXV */
119 /* C-RXV */
141 #define MT_CRXV_HE_RU2			GENMASK(26, 18)
187 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
193 #define MT_TXD1_OWN_MAC			GENMASK(30, 25)
203 #define MT_TXD2_MAX_TX_TIME		GENMASK(25, 16)
242 #define MT_TXD6_FIXED_BW		BIT(25)
258 #define MT_TXD7_CTXD_CNT		GENMASK(25, 22)
272 /* VHT/HE only use bits 0-3 */
276 #define MT_TXFREE0_MSDU_CNT		GENMASK(25, 16)
290 #define MT_TXS0_AMPDU			BIT(25)
297 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
300 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
328 #define MT_TXS5_F0_TX_COUNT		GENMASK(29, 25)