mediatek/mt76/mt76_connac2_mac.h

1 /* SPDX-License-Identifier: ISC */
23 	MT_HIF0 = 0x0,
25 	MT_LMAC_AC00 = 0x0,
29 	MT_LMAC_ALTX0 = 0x10,
35 #define MT_TX_FREE_MSDU_CNT		GENMASK(9, 0)
37 #define MT_TX_FREE_COUNT		GENMASK(12, 0)
38 /* 0: success, others: dropped */
41 #define MT_TX_FREE_PAIR			BIT(31)
43 #define MT_TX_FREE_RATE			GENMASK(13, 0)
45 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
48 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
50 #define MT_TXD1_LONG_FORMAT		BIT(31)
60 #define MT_TXD1_WLAN_IDX		GENMASK(9, 0)
62 #define MT_TXD2_FIX_RATE		BIT(31)
76 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
78 #define MT_TXD3_SN_VALID		BIT(31)
90 #define MT_TXD3_NO_ACK			BIT(0)
92 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
94 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
100 #define MT_TXD5_PID			GENMASK(7, 0)
102 #define MT_TXD6_TX_IBF			BIT(31)
112 #define MT_TXD6_BW			GENMASK(1, 0)
114 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
123 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
126 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
133 /* VHT/HE only use bits 0-3 */
134 #define MT_TX_RATE_IDX			GENMASK(5, 0)
136 #define MT_TXS0_FIXED_RATE		BIT(31)
153 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
155 #define MT_TXS1_SEQNO			GENMASK(31, 20)
158 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
160 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
164 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
166 #define MT_TXS3_PID			GENMASK(31, 24)
167 #define MT_TXS3_ANT_ID			GENMASK(23, 0)
169 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
172 #define MT_TXS5_MPDU_TX_BYTE		GENMASK(22, 0)
173 #define MT_TXS5_MPDU_TX_CNT		GENMASK(31, 23)
175 #define MT_TXS6_MPDU_FAIL_CNT		GENMASK(31, 23)
176 #define MT_TXS7_MPDU_RETRY_BYTE		GENMASK(22, 0)
177 #define MT_TXS7_MPDU_RETRY_CNT		GENMASK(31, 23)
180 #define MT_RXD0_LENGTH			GENMASK(15, 0)
182 #define MT_RXD0_PKT_TYPE		GENMASK(31, 27)
189 #define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(9, 0)
205 #define MT_RXD1_NORMAL_SEC_DONE		BIT(31)
208 #define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
225 #define MT_RXD2_NORMAL_BF_REPORT	BIT(31)
228 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
229 #define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
231 #define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)
239 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
244 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
247 #define MT_RXD3_NORMAL_U2M		BIT(0)
248 #define MT_RXD3_NORMAL_HTC_VLD		BIT(0)
261 #define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)
264 #define MT_RXD6_FRAME_CONTROL		GENMASK(15, 0)
265 #define MT_RXD6_TA_LO			GENMASK(31, 16)
267 #define MT_RXD7_TA_HI			GENMASK(31, 0)
269 #define MT_RXD8_SEQ_CTRL		GENMASK(15, 0)
270 #define MT_RXD8_QOS_CTL			GENMASK(31, 16)
272 #define MT_RXD9_HT_CONTROL		GENMASK(31, 0)
274 /* P-RXV DW0 */
275 #define MT_PRXV_TX_RATE			GENMASK(6, 0)
281 #define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)
290 /* P-RXV DW1 */
291 #define MT_PRXV_RCPI3			GENMASK(31, 24)
294 #define MT_PRXV_RCPI0			GENMASK(7, 0)
295 #define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)
297 /* C-RXV */
298 #define MT_CRXV_HT_STBC			GENMASK(1, 0)
306 #define MT_CRXV_HE_UPLINK		BIT(31)
308 #define MT_CRXV_HE_RU0			GENMASK(7, 0)
311 #define MT_CRXV_HE_RU3			GENMASK(31, 24)
320 #define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)
326 #define MT_CRXV_FOE_LO		GENMASK(31, 19)
327 #define MT_CRXV_FOE_HI		GENMASK(6, 0)
333 #define MT_CT_INFO_APPLY_TXD		BIT(0)
341 	MT_TX_MCU_PORT_RX_Q0 = 0x20,
345 	MT_TX_MCU_PORT_RX_FWDL = 0x3e