14 	val = readl(dev->mmio.regs + offset);  in mt76_mmio_rr()
23 	writel(val, dev->mmio.regs + offset);  in mt76_mmio_wr()
36 	__iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));  in mt76_mmio_write_copy()
42 	__ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));  in mt76_mmio_read_copy()
74 	spin_lock_irqsave(&dev->mmio.irq_lock, flags);  in mt76_set_irq_mask()
75 	dev->mmio.irqmask &= ~clear;  in mt76_set_irq_mask()
76 	dev->mmio.irqmask |= set;  in mt76_set_irq_mask()
78 		if (mtk_wed_device_active(&dev->mmio.wed))  in mt76_set_irq_mask()
79 			mtk_wed_device_irq_set_mask(&dev->mmio.wed,  in mt76_set_irq_mask()
80 						    dev->mmio.irqmask);  in mt76_set_irq_mask()
82 			mt76_mmio_wr(dev, addr, dev->mmio.irqmask);  in mt76_set_irq_mask()
84 	spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);  in mt76_set_irq_mask()
91 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);  in mt76_mmio_wed_release_rx_buf()
113 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);  in mt76_mmio_wed_init_rx_buf()
166 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);  in mt76_mmio_wed_offload_enable()
178 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);  in mt76_mmio_wed_offload_disable()
188 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);  in mt76_mmio_wed_reset_complete()
190 	complete(&dev->mmio.wed_reset_complete);  in mt76_mmio_wed_reset_complete()
209 	dev->mmio.regs = regs;  in mt76_mmio_init()
211 	spin_lock_init(&dev->mmio.irq_lock);  in mt76_mmio_init()