Lines Matching +full:adc +full:- +full:alt +full:- +full:channel
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
23 u16 version = le16_to_cpu(ah->eeprom.map4k.baseEepHeader.version); in ath9k_hw_4k_get_eeprom_ver()
31 u16 version = le16_to_cpu(ah->eeprom.map4k.baseEepHeader.version); in ath9k_hw_4k_get_eeprom_rev()
40 u16 *eep_data = (u16 *)&ah->eeprom.map4k; in __ath9k_hw_4k_fill_eeprom()
54 u16 *eep_data = (u16 *)&ah->eeprom.map4k; in __ath9k_hw_usb_4k_fill_eeprom()
69 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_4k_fill_eeprom()
79 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); in ath9k_dump_4k_modal_eeprom()
80 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ath9k_dump_4k_modal_eeprom()
81 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); in ath9k_dump_4k_modal_eeprom()
82 PR_EEP("Switch Settle", modal_hdr->switchSettling); in ath9k_dump_4k_modal_eeprom()
83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); in ath9k_dump_4k_modal_eeprom()
84 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); in ath9k_dump_4k_modal_eeprom()
85 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); in ath9k_dump_4k_modal_eeprom()
86 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize); in ath9k_dump_4k_modal_eeprom()
87 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]); in ath9k_dump_4k_modal_eeprom()
88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); in ath9k_dump_4k_modal_eeprom()
89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); in ath9k_dump_4k_modal_eeprom()
90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); in ath9k_dump_4k_modal_eeprom()
91 PR_EEP("CCA Threshold)", modal_hdr->thresh62); in ath9k_dump_4k_modal_eeprom()
92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); in ath9k_dump_4k_modal_eeprom()
93 PR_EEP("xpdGain", modal_hdr->xpdGain); in ath9k_dump_4k_modal_eeprom()
94 PR_EEP("External PD", modal_hdr->xpd); in ath9k_dump_4k_modal_eeprom()
95 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); in ath9k_dump_4k_modal_eeprom()
96 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); in ath9k_dump_4k_modal_eeprom()
97 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); in ath9k_dump_4k_modal_eeprom()
98 PR_EEP("O/D Bias Version", modal_hdr->version); in ath9k_dump_4k_modal_eeprom()
99 PR_EEP("CCK OutputBias", modal_hdr->ob_0); in ath9k_dump_4k_modal_eeprom()
100 PR_EEP("BPSK OutputBias", modal_hdr->ob_1); in ath9k_dump_4k_modal_eeprom()
101 PR_EEP("QPSK OutputBias", modal_hdr->ob_2); in ath9k_dump_4k_modal_eeprom()
102 PR_EEP("16QAM OutputBias", modal_hdr->ob_3); in ath9k_dump_4k_modal_eeprom()
103 PR_EEP("64QAM OutputBias", modal_hdr->ob_4); in ath9k_dump_4k_modal_eeprom()
104 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0); in ath9k_dump_4k_modal_eeprom()
105 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1); in ath9k_dump_4k_modal_eeprom()
106 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2); in ath9k_dump_4k_modal_eeprom()
107 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3); in ath9k_dump_4k_modal_eeprom()
108 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4); in ath9k_dump_4k_modal_eeprom()
109 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0); in ath9k_dump_4k_modal_eeprom()
110 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1); in ath9k_dump_4k_modal_eeprom()
111 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2); in ath9k_dump_4k_modal_eeprom()
112 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3); in ath9k_dump_4k_modal_eeprom()
113 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4); in ath9k_dump_4k_modal_eeprom()
114 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); in ath9k_dump_4k_modal_eeprom()
115 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); in ath9k_dump_4k_modal_eeprom()
116 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); in ath9k_dump_4k_modal_eeprom()
117 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); in ath9k_dump_4k_modal_eeprom()
118 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); in ath9k_dump_4k_modal_eeprom()
119 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); in ath9k_dump_4k_modal_eeprom()
120 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); in ath9k_dump_4k_modal_eeprom()
121 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]); in ath9k_dump_4k_modal_eeprom()
122 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]); in ath9k_dump_4k_modal_eeprom()
123 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1); in ath9k_dump_4k_modal_eeprom()
124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); in ath9k_dump_4k_modal_eeprom()
125 PR_EEP("TX Diversity", modal_hdr->tx_diversity); in ath9k_dump_4k_modal_eeprom()
133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; in ath9k_hw_4k_dump_eeprom()
134 struct base_eep_header_4k *pBase = &eep->baseEepHeader; in ath9k_hw_4k_dump_eeprom()
135 u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber); in ath9k_hw_4k_dump_eeprom()
138 len += scnprintf(buf + len, size - len, in ath9k_hw_4k_dump_eeprom()
141 &eep->modalHeader); in ath9k_hw_4k_dump_eeprom()
147 PR_EEP("Checksum", le16_to_cpu(pBase->checksum)); in ath9k_hw_4k_dump_eeprom()
148 PR_EEP("Length", le16_to_cpu(pBase->length)); in ath9k_hw_4k_dump_eeprom()
149 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); in ath9k_hw_4k_dump_eeprom()
150 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); in ath9k_hw_4k_dump_eeprom()
151 PR_EEP("TX Mask", pBase->txMask); in ath9k_hw_4k_dump_eeprom()
152 PR_EEP("RX Mask", pBase->rxMask); in ath9k_hw_4k_dump_eeprom()
153 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); in ath9k_hw_4k_dump_eeprom()
154 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); in ath9k_hw_4k_dump_eeprom()
155 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & in ath9k_hw_4k_dump_eeprom()
157 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & in ath9k_hw_4k_dump_eeprom()
159 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & in ath9k_hw_4k_dump_eeprom()
161 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & in ath9k_hw_4k_dump_eeprom()
163 PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN)); in ath9k_hw_4k_dump_eeprom()
167 PR_EEP("TX Gain type", pBase->txGainType); in ath9k_hw_4k_dump_eeprom()
169 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", in ath9k_hw_4k_dump_eeprom()
170 pBase->macAddr); in ath9k_hw_4k_dump_eeprom()
188 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; in ath9k_hw_4k_check_eeprom()
198 el = swab16((__force u16)eep->baseEepHeader.length); in ath9k_hw_4k_check_eeprom()
200 el = le16_to_cpu(eep->baseEepHeader.length); in ath9k_hw_4k_check_eeprom()
204 return -EINVAL; in ath9k_hw_4k_check_eeprom()
207 EEPROM_FIELD_SWAB16(eep->baseEepHeader.length); in ath9k_hw_4k_check_eeprom()
208 EEPROM_FIELD_SWAB16(eep->baseEepHeader.checksum); in ath9k_hw_4k_check_eeprom()
209 EEPROM_FIELD_SWAB16(eep->baseEepHeader.version); in ath9k_hw_4k_check_eeprom()
210 EEPROM_FIELD_SWAB16(eep->baseEepHeader.regDmn[0]); in ath9k_hw_4k_check_eeprom()
211 EEPROM_FIELD_SWAB16(eep->baseEepHeader.regDmn[1]); in ath9k_hw_4k_check_eeprom()
212 EEPROM_FIELD_SWAB16(eep->baseEepHeader.rfSilent); in ath9k_hw_4k_check_eeprom()
213 EEPROM_FIELD_SWAB16(eep->baseEepHeader.blueToothOptions); in ath9k_hw_4k_check_eeprom()
214 EEPROM_FIELD_SWAB16(eep->baseEepHeader.deviceCap); in ath9k_hw_4k_check_eeprom()
215 EEPROM_FIELD_SWAB32(eep->modalHeader.antCtrlCommon); in ath9k_hw_4k_check_eeprom()
218 EEPROM_FIELD_SWAB32(eep->modalHeader.antCtrlChain[i]); in ath9k_hw_4k_check_eeprom()
222 eep->modalHeader.spurChans[i].spurChan); in ath9k_hw_4k_check_eeprom()
227 return -EINVAL; in ath9k_hw_4k_check_eeprom()
237 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; in ath9k_hw_4k_get_eeprom()
238 struct modal_eep_4k_header *pModal = &eep->modalHeader; in ath9k_hw_4k_get_eeprom()
239 struct base_eep_header_4k *pBase = &eep->baseEepHeader; in ath9k_hw_4k_get_eeprom()
243 return pModal->noiseFloorThreshCh[0]; in ath9k_hw_4k_get_eeprom()
245 return get_unaligned_be16(pBase->macAddr); in ath9k_hw_4k_get_eeprom()
247 return get_unaligned_be16(pBase->macAddr + 2); in ath9k_hw_4k_get_eeprom()
249 return get_unaligned_be16(pBase->macAddr + 4); in ath9k_hw_4k_get_eeprom()
251 return le16_to_cpu(pBase->regDmn[0]); in ath9k_hw_4k_get_eeprom()
253 return le16_to_cpu(pBase->deviceCap); in ath9k_hw_4k_get_eeprom()
255 return pBase->opCapFlags; in ath9k_hw_4k_get_eeprom()
257 return le16_to_cpu(pBase->rfSilent); in ath9k_hw_4k_get_eeprom()
259 return pModal->ob_0; in ath9k_hw_4k_get_eeprom()
261 return pModal->db1_1; in ath9k_hw_4k_get_eeprom()
263 return pBase->txMask; in ath9k_hw_4k_get_eeprom()
265 return pBase->rxMask; in ath9k_hw_4k_get_eeprom()
271 return pModal->version; in ath9k_hw_4k_get_eeprom()
273 return pModal->antdiv_ctl1; in ath9k_hw_4k_get_eeprom()
275 return pBase->txGainType; in ath9k_hw_4k_get_eeprom()
277 return pModal->antennaGainCh[0]; in ath9k_hw_4k_get_eeprom()
287 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; in ath9k_hw_set_4k_power_cal_table()
298 xpdMask = pEepData->modalHeader.xpdGain; in ath9k_hw_set_4k_power_cal_table()
302 pEepData->modalHeader.pdGainOverlap; in ath9k_hw_set_4k_power_cal_table()
307 pCalBChans = pEepData->calFreqPier2G; in ath9k_hw_set_4k_power_cal_table()
313 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { in ath9k_hw_set_4k_power_cal_table()
317 (u16)(AR5416_PD_GAINS_IN_MASK - i); in ath9k_hw_set_4k_power_cal_table()
324 (numXpdGain - 1) & 0x3); in ath9k_hw_set_4k_power_cal_table()
335 if (pEepData->baseEepHeader.txMask & (1 << i)) { in ath9k_hw_set_4k_power_cal_table()
336 pRawDataset = pEepData->calPierData2G[i]; in ath9k_hw_set_4k_power_cal_table()
395 pEepData->ctlIndex[i]) \ in ath9k_hw_set_4k_power_per_rate_table()
397 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) in ath9k_hw_set_4k_power_per_rate_table()
408 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; in ath9k_hw_set_4k_power_per_rate_table()
426 scaledPower = powerLimit - antenna_reduction; in ath9k_hw_set_4k_power_per_rate_table()
428 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; in ath9k_hw_set_4k_power_per_rate_table()
432 pEepData->calTargetPowerCck, in ath9k_hw_set_4k_power_per_rate_table()
436 pEepData->calTargetPower2G, in ath9k_hw_set_4k_power_per_rate_table()
440 pEepData->calTargetPower2GHT20, in ath9k_hw_set_4k_power_per_rate_table()
447 pEepData->calTargetPower2GHT40, in ath9k_hw_set_4k_power_per_rate_table()
451 pEepData->calTargetPowerCck, in ath9k_hw_set_4k_power_per_rate_table()
455 pEepData->calTargetPower2G, in ath9k_hw_set_4k_power_per_rate_table()
474 pEepData->ctlIndex[i]; i++) { in ath9k_hw_set_4k_power_per_rate_table()
477 rep = &(pEepData->ctlData[i]); in ath9k_hw_set_4k_power_per_rate_table()
481 rep->ctlEdges[ in ath9k_hw_set_4k_power_per_rate_table()
482 ar5416_get_ntxchains(ah->txchainmask) - 1], in ath9k_hw_set_4k_power_per_rate_table()
584 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; in ath9k_hw_4k_set_txpower()
585 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; in ath9k_hw_4k_set_txpower()
593 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; in ath9k_hw_4k_set_txpower()
602 regulatory->max_power_level = 0; in ath9k_hw_4k_set_txpower()
607 if (ratesArray[i] > regulatory->max_power_level) in ath9k_hw_4k_set_txpower()
608 regulatory->max_power_level = ratesArray[i]; in ath9k_hw_4k_set_txpower()
615 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; in ath9k_hw_4k_set_txpower()
683 if (ah->tpc_enabled) { in ath9k_hw_4k_set_txpower()
706 le32_to_cpu(pModal->antCtrlChain[0]), 0); in ath9k_hw_4k_set_gain()
709 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
710 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF), in ath9k_hw_4k_set_gain()
714 txRxAttenLocal = pModal->txRxAttenCh[0]; in ath9k_hw_4k_set_gain()
717 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); in ath9k_hw_4k_set_gain()
719 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); in ath9k_hw_4k_set_gain()
722 pModal->xatten2Margin[0]); in ath9k_hw_4k_set_gain()
724 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); in ath9k_hw_4k_set_gain()
729 pModal->bswMargin[0]); in ath9k_hw_4k_set_gain()
731 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); in ath9k_hw_4k_set_gain()
734 pModal->xatten2Margin[0]); in ath9k_hw_4k_set_gain()
737 pModal->xatten2Db[0]); in ath9k_hw_4k_set_gain()
743 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); in ath9k_hw_4k_set_gain()
748 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); in ath9k_hw_4k_set_gain()
754 * given the channel value.
759 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_4k_set_board_values()
761 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; in ath9k_hw_4k_set_board_values()
762 struct base_eep_header_4k *pBase = &eep->baseEepHeader; in ath9k_hw_4k_set_board_values()
769 pModal = &eep->modalHeader; in ath9k_hw_4k_set_board_values()
772 REG_WRITE(ah, AR_PHY_SWITCH_COM, le32_to_cpu(pModal->antCtrlCommon)); in ath9k_hw_4k_set_board_values()
778 if (pModal->version >= 3) { in ath9k_hw_4k_set_board_values()
779 ant_div_control1 = pModal->antdiv_ctl1; in ath9k_hw_4k_set_board_values()
780 ant_div_control2 = pModal->antdiv_ctl2; in ath9k_hw_4k_set_board_values()
807 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ath9k_hw_4k_set_board_values()
810 * set MAIN to LNA1 and ALT to LNA2 initially. in ath9k_hw_4k_set_board_values()
826 if (pModal->version >= 2) { in ath9k_hw_4k_set_board_values()
827 ob[0] = pModal->ob_0; in ath9k_hw_4k_set_board_values()
828 ob[1] = pModal->ob_1; in ath9k_hw_4k_set_board_values()
829 ob[2] = pModal->ob_2; in ath9k_hw_4k_set_board_values()
830 ob[3] = pModal->ob_3; in ath9k_hw_4k_set_board_values()
831 ob[4] = pModal->ob_4; in ath9k_hw_4k_set_board_values()
833 db1[0] = pModal->db1_0; in ath9k_hw_4k_set_board_values()
834 db1[1] = pModal->db1_1; in ath9k_hw_4k_set_board_values()
835 db1[2] = pModal->db1_2; in ath9k_hw_4k_set_board_values()
836 db1[3] = pModal->db1_3; in ath9k_hw_4k_set_board_values()
837 db1[4] = pModal->db1_4; in ath9k_hw_4k_set_board_values()
839 db2[0] = pModal->db2_0; in ath9k_hw_4k_set_board_values()
840 db2[1] = pModal->db2_1; in ath9k_hw_4k_set_board_values()
841 db2[2] = pModal->db2_2; in ath9k_hw_4k_set_board_values()
842 db2[3] = pModal->db2_3; in ath9k_hw_4k_set_board_values()
843 db2[4] = pModal->db2_4; in ath9k_hw_4k_set_board_values()
844 } else if (pModal->version == 1) { in ath9k_hw_4k_set_board_values()
845 ob[0] = pModal->ob_0; in ath9k_hw_4k_set_board_values()
846 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; in ath9k_hw_4k_set_board_values()
847 db1[0] = pModal->db1_0; in ath9k_hw_4k_set_board_values()
848 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; in ath9k_hw_4k_set_board_values()
849 db2[0] = pModal->db2_0; in ath9k_hw_4k_set_board_values()
850 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; in ath9k_hw_4k_set_board_values()
855 ob[i] = pModal->ob_0; in ath9k_hw_4k_set_board_values()
856 db1[i] = pModal->db1_0; in ath9k_hw_4k_set_board_values()
857 db2[i] = pModal->db1_0; in ath9k_hw_4k_set_board_values()
970 pModal->switchSettling); in ath9k_hw_4k_set_board_values()
972 pModal->adcDesiredSize); in ath9k_hw_4k_set_board_values()
975 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | in ath9k_hw_4k_set_board_values()
976 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | in ath9k_hw_4k_set_board_values()
977 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | in ath9k_hw_4k_set_board_values()
978 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON), 0); in ath9k_hw_4k_set_board_values()
981 pModal->txEndToRxOn); in ath9k_hw_4k_set_board_values()
985 pModal->txEndToRxOn); in ath9k_hw_4k_set_board_values()
987 pModal->thresh62); in ath9k_hw_4k_set_board_values()
989 pModal->thresh62); in ath9k_hw_4k_set_board_values()
993 pModal->txFrameToDataStart); in ath9k_hw_4k_set_board_values()
995 pModal->txFrameToPaOn); in ath9k_hw_4k_set_board_values()
1002 pModal->swSettleHt40); in ath9k_hw_4k_set_board_values()
1007 bb_desired_scale = (pModal->bb_scale_smrt_antenna & in ath9k_hw_4k_set_board_values()
1009 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) { in ath9k_hw_4k_set_board_values()
1036 return le16_to_cpu(ah->eeprom.map4k.modalHeader.spurChans[i].spurChan); in ath9k_hw_4k_get_spur_channel()
1041 return ah->eeprom.map4k.baseEepHeader.eepMisc; in ath9k_hw_4k_get_eepmisc()